Lines Matching refs:temp1
411 #define temp1 r2 /* careful, it overlaps with input registers */
463 add temp1=temp2, regs // struct ia64_sal_os_state on MCA or INIT stack
466 mov regs=temp1 // save the start of sos
467 st8 [temp1]=r1,16 // os_gp
470 st8 [temp1]=r9,16 // sal_proc
474 st8 [temp1]=r18 // proc_state_param
477 add temp1=SOS(SAL_RA), regs
480 st8 [temp1]=r12,16 // sal_ra
484 st8 [temp1]=r17,16 // pal_min_state
488 st8 [temp1]=r6,16 // prev_IA64_KR_CURRENT_STACK
492 st8 [temp1]=r12,16 // cr.isr
496 st8 [temp1]=r12,16 // cr.itir
500 st8 [temp1]=r12 // cr.iim
504 add temp1=SOS(OS_STATUS), regs
508 st8 [temp1]=r12 // os_status, default is cold boot
517 add temp1=PT(B6), regs
522 st8 [temp1]=temp3,PT(AR_CSD)-PT(B6) // save b6
528 st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD) // save ar.csd
533 st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT) // save ar.unat
538 st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT) // save ar.rnat
547 st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS) // save loadrs
551 st8 [temp1]=temp3,PT(F7)-PT(AR_CCV) // save ar.ccv
554 stf.spill [temp1]=f7,PT(F9)-PT(F7)
557 stf.spill [temp1]=f9,PT(F11)-PT(F9)
560 stf.spill [temp1]=f11
566 add temp1=SW(F2), regs
569 stf.spill [temp1]=f2,32
572 stf.spill [temp1]=f4,32
575 stf.spill [temp1]=f12,32
578 stf.spill [temp1]=f14,32
581 stf.spill [temp1]=f16,32
584 stf.spill [temp1]=f18,32
587 stf.spill [temp1]=f20,32
590 stf.spill [temp1]=f22,32
593 stf.spill [temp1]=f24,32
596 stf.spill [temp1]=f26,32
599 stf.spill [temp1]=f28,32
602 stf.spill [temp1]=f30,SW(B2)-SW(F30)
607 st8 [temp1]=temp3,16 // save b2
612 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
616 st8 [temp1]=temp3 // save ar.lc
724 add temp1=SW(F2), regs
727 ldf.fill f2=[temp1],32
730 ldf.fill f4=[temp1],32
733 ldf.fill f12=[temp1],32
736 ldf.fill f14=[temp1],32
739 ldf.fill f16=[temp1],32
742 ldf.fill f18=[temp1],32
745 ldf.fill f20=[temp1],32
748 ldf.fill f22=[temp1],32
751 ldf.fill f24=[temp1],32
754 ldf.fill f26=[temp1],32
757 ldf.fill f28=[temp1],32
760 ldf.fill f30=[temp1],SW(B2)-SW(F30)
763 ld8 temp3=[temp1],16 // restore b2
768 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
773 ld8 temp3=[temp1] // restore ar.lc
781 add temp1=PT(B6), regs
784 ld8 temp3=[temp1],PT(AR_CSD)-PT(B6) // restore b6
789 ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD) // restore ar.csd
794 ld8 temp3=[temp1] // restore ar.unat
795 add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1
801 ld8 temp3=[temp1],PT(F6)-PT(AR_CCV) // restore ar.ccv
806 ldf.fill f6=[temp1],PT(F8)-PT(F6)
809 ldf.fill f8=[temp1],PT(F10)-PT(F8)
812 ldf.fill f10=[temp1]
818 add temp1=SOS(SAL_RA), regs
821 ld8 r12=[temp1],16 // sal_ra
824 ld8 r22=[temp1],16 // pal_min_state, virtual
827 ld8 r16=[temp1],16 // prev_IA64_KR_CURRENT_STACK
830 ld8 temp3=[temp1],16 // cr.isr
835 ld8 temp3=[temp1],16 // cr.itir
840 ld8 temp3=[temp1] // cr.iim
842 add temp1=SOS(OS_STATUS), regs
849 ld8 r8=[temp1] // os_status
918 GET_IA64_MCA_DATA(temp1)
921 add temp2=temp2, temp1 // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack
922 add regs=regs, temp1 // struct pt_regs on MCA or INIT stack
928 dep temp1=-1,ms,62,2 // set region 6
931 st8 [temp2]=temp1 // pal_min_state, virtual
972 LOAD_PHYSICAL(p0,temp1,1f)
976 mov cr.iip=temp1
984 add temp1=PT(LOADRS), regs
986 ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS) // restore loadrs
988 ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE) // restore ar.bspstore
992 ld8 temp4=[temp1] // restore ar.rnat
1021 GET_IA64_MCA_DATA(temp1)
1023 add r12=temp1, temp3 // kernel stack pointer on MCA/INIT stack
1024 add r13=temp1, r3 // set current to start of MCA/INIT stack
1025 add r20=temp1, r3 // physical start of MCA/INIT stack
1072 #undef temp1