Lines Matching refs:i_i
31 int i_d, i_i;
39 i_d = i_i = 0;
45 i_tbl[i_i].addr = 0;
46 i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
55 i_tbl[i_i].addr = addr;
56 i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
64 i_tbl[i_i].addr = addr;
65 i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
74 i_tbl[i_i].addr = L1_CODE_START;
75 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
83 i_tbl[i_i].addr = COREB_L1_CODE_START;
84 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
88 first_switched_icplb = i_i;
95 while (i_i < MAX_CPLBS)
96 i_tbl[i_i++].data = 0;
102 int i_d, i_i;
155 i_i = 0;
157 icplb_bounds[i_i].eaddr = uncached_end;
158 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
163 icplb_bounds[i_i].eaddr = _ramend;
164 icplb_bounds[i_i++].data = 0;
167 icplb_bounds[i_i].eaddr = physical_mem_end;
168 icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
172 icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
173 icplb_bounds[i_i++].data = 0;
175 icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
176 icplb_bounds[i_i++].data = SDRAM_EBIU;
178 icplb_bounds[i_i].eaddr = BOOT_ROM_START;
179 icplb_bounds[i_i++].data = 0;
181 icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
182 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
186 icplb_bounds[i_i].eaddr = L2_START;
187 icplb_bounds[i_i++].data = 0;
189 icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
190 icplb_bounds[i_i++].data = L2_IMEMORY;
192 icplb_nr_bounds = i_i;