Lines Matching defs:lch
70 void (*callback)(int lch, u16 ch_status, void *data);
150 static inline void disable_lnk(int lch);
151 static void omap_disable_channel_irq(int lch);
152 static inline void omap_enable_channel_irq(int lch);
210 static void clear_lch_regs(int lch)
213 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
219 void omap_set_dma_priority(int lch, int dst_port, int priority)
251 ccr = dma_read(CCR(lch));
256 dma_write(ccr, CCR(lch));
261 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
267 l = dma_read(CSDP(lch));
270 dma_write(l, CSDP(lch));
275 ccr = dma_read(CCR(lch));
279 dma_write(ccr, CCR(lch));
281 ccr = dma_read(CCR2(lch));
285 dma_write(ccr, CCR2(lch));
291 val = dma_read(CCR(lch));
316 dma_write(val, CCR(lch));
319 dma_write(elem_count, CEN(lch));
320 dma_write(frame_count, CFN(lch));
324 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
331 w = dma_read(CCR2(lch));
346 dma_write(w, CCR2(lch));
348 w = dma_read(LCH_CTRL(lch));
352 dma_write((u16)color, COLOR_L(lch));
353 dma_write((u16)(color >> 16), COLOR_U(lch));
356 dma_write(w, LCH_CTRL(lch));
362 val = dma_read(CCR(lch));
377 dma_write(val, CCR(lch));
380 dma_write(color, COLOR(lch));
385 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
390 csdp = dma_read(CSDP(lch));
393 dma_write(csdp, CSDP(lch));
398 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
403 l = dma_read(LCH_CTRL(lch));
406 dma_write(l, LCH_CTRL(lch));
412 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
421 w = dma_read(CSDP(lch));
424 dma_write(w, CSDP(lch));
427 l = dma_read(CCR(lch));
430 dma_write(l, CCR(lch));
433 dma_write(src_start >> 16, CSSA_U(lch));
434 dma_write((u16)src_start, CSSA_L(lch));
438 dma_write(src_start, CSSA(lch));
440 dma_write(src_ei, CSEI(lch));
441 dma_write(src_fi, CSFI(lch));
445 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
447 omap_set_dma_transfer_params(lch, params->data_type,
451 omap_set_dma_src_params(lch, params->src_port,
455 omap_set_dma_dest_params(lch, params->dst_port,
459 omap_dma_set_prio_lch(lch, params->read_prio,
464 void omap_set_dma_src_index(int lch, int eidx, int fidx)
469 dma_write(eidx, CSEI(lch));
470 dma_write(fidx, CSFI(lch));
474 void omap_set_dma_src_data_pack(int lch, int enable)
478 l = dma_read(CSDP(lch));
482 dma_write(l, CSDP(lch));
486 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
491 l = dma_read(CSDP(lch));
527 dma_write(l, CSDP(lch));
532 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
539 l = dma_read(CSDP(lch));
542 dma_write(l, CSDP(lch));
545 l = dma_read(CCR(lch));
548 dma_write(l, CCR(lch));
551 dma_write(dest_start >> 16, CDSA_U(lch));
552 dma_write(dest_start, CDSA_L(lch));
556 dma_write(dest_start, CDSA(lch));
558 dma_write(dst_ei, CDEI(lch));
559 dma_write(dst_fi, CDFI(lch));
563 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
568 dma_write(eidx, CDEI(lch));
569 dma_write(fidx, CDFI(lch));
573 void omap_set_dma_dest_data_pack(int lch, int enable)
577 l = dma_read(CSDP(lch));
581 dma_write(l, CSDP(lch));
585 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
590 l = dma_read(CSDP(lch));
623 dma_write(l, CSDP(lch));
627 static inline void omap_enable_channel_irq(int lch)
633 status = dma_read(CSR(lch));
635 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
638 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
641 static void omap_disable_channel_irq(int lch)
644 dma_write(0, CICR(lch));
647 void omap_enable_dma_irq(int lch, u16 bits)
649 dma_chan[lch].enabled_irqs |= bits;
653 void omap_disable_dma_irq(int lch, u16 bits)
655 dma_chan[lch].enabled_irqs &= ~bits;
659 static inline void enable_lnk(int lch)
663 l = dma_read(CLNK_CTRL(lch));
669 if (dma_chan[lch].next_lch != -1)
670 l = dma_chan[lch].next_lch | (1 << 15);
674 if (dma_chan[lch].next_linked_ch != -1)
675 l = dma_chan[lch].next_linked_ch | (1 << 15);
678 dma_write(l, CLNK_CTRL(lch));
681 static inline void disable_lnk(int lch)
685 l = dma_read(CLNK_CTRL(lch));
689 dma_write(0, CICR(lch));
695 omap_disable_channel_irq(lch);
700 dma_write(l, CLNK_CTRL(lch));
701 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
704 static inline void omap2_enable_irq_lch(int lch)
714 val |= 1 << lch;
719 static inline void omap2_disable_irq_lch(int lch)
729 val &= ~(1 << lch);
735 void (*callback)(int lch, u16 ch_status, void *data),
814 void omap_free_dma(int lch)
818 if (dma_chan[lch].dev_id == -1) {
820 lch);
826 dma_write(0, CICR(lch));
828 dma_write(0, CCR(lch));
832 omap2_disable_irq_lch(lch);
835 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
836 dma_write(1 << lch, IRQSTATUS_L0);
839 dma_write(0, CICR(lch));
842 dma_write(0, CCR(lch));
843 omap_clear_dma(lch);
847 dma_chan[lch].dev_id = -1;
848 dma_chan[lch].next_lch = -1;
849 dma_chan[lch].callback = NULL;
890 * @param lch
897 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
902 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
906 l = dma_read(CCR(lch));
913 dma_write(l, CCR(lch));
923 void omap_clear_dma(int lch)
932 l = dma_read(CCR(lch));
934 dma_write(l, CCR(lch));
937 l = dma_read(CSR(lch));
942 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
951 void omap_start_dma(int lch)
960 dma_write(0, CPC(lch));
962 dma_write(0, CDAC(lch));
964 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
968 dma_chan_link_map[lch] = 1;
970 enable_lnk(lch);
973 cur_lch = dma_chan[lch].next_lch;
991 /* Errata: Need to write lch even if not using chaining */
992 dma_write(lch, CLNK_CTRL(lch));
995 omap_enable_channel_irq(lch);
997 l = dma_read(CCR(lch));
1004 dma_write(l, CCR(lch));
1006 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1010 void omap_stop_dma(int lch)
1016 dma_write(0, CICR(lch));
1018 l = dma_read(CCR(lch));
1031 l = dma_read(CCR(lch));
1033 dma_write(l, CCR(lch));
1036 l = dma_read(CCR(lch));
1041 l = dma_read(CCR(lch));
1045 "lch %d\n", lch);
1050 dma_write(l, CCR(lch));
1053 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1054 int next_lch, cur_lch = lch;
1072 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1080 int omap_set_dma_callback(int lch,
1081 void (*callback)(int lch, u16 ch_status, void *data),
1086 if (lch < 0)
1090 if (dma_chan[lch].dev_id == -1) {
1095 dma_chan[lch].callback = callback;
1096 dma_chan[lch].data = data;
1111 dma_addr_t omap_get_dma_src_pos(int lch)
1116 offset = dma_read(CPC(lch));
1118 offset = dma_read(CSAC(lch));
1125 offset = dma_read(CSAC(lch));
1128 offset |= (dma_read(CSSA_U(lch)) << 16);
1142 dma_addr_t omap_get_dma_dst_pos(int lch)
1147 offset = dma_read(CPC(lch));
1149 offset = dma_read(CDAC(lch));
1156 offset = dma_read(CDAC(lch));
1159 offset |= (dma_read(CDSA_U(lch)) << 16);
1165 int omap_get_dma_active_status(int lch)
1167 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1173 int lch;
1179 for (lch = 0; lch < dma_chan_count; lch++)
1180 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1302 void (*callback) (int lch, u16 ch_status,
1516 u32 l, lch;
1549 lch = channels[dma_linked_lch[chain_id].q_tail];
1552 dma_chan[lch].data = callbk_data;
1559 dma_write(src_start, CSSA(lch));
1561 dma_write(dest_start, CDSA(lch));
1564 dma_write(elem_count, CEN(lch));
1565 dma_write(frame_count, CFN(lch));
1580 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1582 enable_lnk(dma_chan[lch].prev_linked_ch);
1583 dma_chan[lch].state = DMA_CH_QUEUED;
1593 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1595 enable_lnk(dma_chan[lch].prev_linked_ch);
1596 dma_chan[lch].state = DMA_CH_QUEUED;
1599 CCR(dma_chan[lch].prev_linked_ch)))) {
1600 disable_lnk(dma_chan[lch].
1607 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1609 enable_lnk(dma_chan[lch].prev_linked_ch);
1610 dma_chan[lch].state = DMA_CH_QUEUED;
1613 omap_enable_channel_irq(lch);
1615 l = dma_read(CCR(lch));
1624 dma_chan[lch].state = DMA_CH_STARTED;
1625 pr_debug("starting %d\n", lch);
1626 dma_write(l, CCR(lch));
1631 dma_write(l, CCR(lch));
1633 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1768 int lch;
1788 lch = channels[dma_linked_lch[chain_id].q_head];
1790 *ei = dma_read(CCEN(lch));
1791 *fi = dma_read(CCFN(lch));
1808 int lch;
1826 lch = channels[dma_linked_lch[chain_id].q_head];
1828 return dma_read(CDAC(lch));
1842 int lch;
1860 lch = channels[dma_linked_lch[chain_id].q_head];
1862 return dma_read(CSAC(lch));
1936 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",