Lines Matching refs:Fld
136 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
138 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
144 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
176 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
178 #define UDCWC_WC Fld (4, 0) /* Write Count */
180 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
336 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
337 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
377 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
468 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
470 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
471 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
491 #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
554 #define HSCR1_AMV Fld (8, 0) /* Address Match Value */
556 #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
621 #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
634 #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
664 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
668 #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
671 #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
676 #define MCDR2_DATA Fld (16, 0) /* reg. DATA */
680 #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
742 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
745 #define SSCR0_FRF Fld (2, 4) /* FRame Format */
755 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
784 #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
866 #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
867 #define RTTR_D Fld (10, 16) /* trim Delete count */
963 #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
1072 #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
1077 #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
1398 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1403 #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1408 #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1413 #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
1416 #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
1427 #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
1430 #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
1431 #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
1433 #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1438 #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
1441 #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
1442 #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
1444 #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1466 Fld (16, ((Nb) Modulo 2)*16)
1472 #define MSC_RT Fld (2, 0) /* ROM/static memory Type */
1484 #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1496 #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1508 #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
1534 Fld (15, (Nb)*16)
1538 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
1543 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
1549 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
1561 #define MDREFR_TRASR Fld (4, 0)
1562 #define MDREFR_DRI Fld (12, 4)
1684 #define DDAR_DS Fld (4, 4) /* Device Select */
1721 #define DDAR_DA Fld (24, 8) /* Device Address */
1793 #define DBT_TC Fld (13, 0) /* Transfer Count */
1861 #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
1862 #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
1863 #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
1864 #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
1865 #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
1928 #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
1955 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
1958 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
1963 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1968 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1974 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1977 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
1982 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1987 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1993 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
2005 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
2015 #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */