Lines Matching defs:IRQ_DC1176_GIC_START
24 #define IRQ_DC1176_GIC_START 32
30 #define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */
31 #define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */
32 #define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */
33 #define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */
34 #define IRQ_DC1176_CORE_PMU (IRQ_DC1176_GIC_START + 7) /* Core PMU interrupt */
35 #define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */
36 #define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */
37 #define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */
38 #define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11)
39 #define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12)
40 #define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
41 #define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
42 #define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
43 #define IRQ_DC1176_SSP (IRQ_DC1176_GIC_START + 17) /* SSP port */
44 #define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
45 #define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
46 #define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */
47 #define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */
49 #define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */
50 #define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */
84 #define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96)