Lines Matching refs:__REG
30 #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
38 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
39 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
40 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
41 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
42 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
43 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
44 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
45 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
46 #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
47 #define PCMD(x) __REG(0x40F50110 + ((x) << 2))
52 #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
53 #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
54 #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
55 #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
56 #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
57 #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
58 #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
59 #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
60 #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
61 #define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
62 #define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
63 #define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
64 #define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
65 #define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
138 #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
139 #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
140 #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
141 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */
142 #define CKENB __REG(0x41340010) /* B Clock Enable Register */
143 #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */