Lines Matching refs:__REG
34 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
35 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
36 #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
37 #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
38 #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
39 #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
40 #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
41 #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
42 #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
43 #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
44 #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
45 #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
46 #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
47 #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
48 #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
49 #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
50 #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
89 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
90 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
91 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
92 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
93 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
94 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
95 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
96 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
97 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
98 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
99 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
100 #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
101 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
103 #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
104 #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
105 #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
106 #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
107 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
108 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
110 #define PCMD0 __REG(0x40F00080 + 0 * 4)
111 #define PCMD1 __REG(0x40F00080 + 1 * 4)
112 #define PCMD2 __REG(0x40F00080 + 2 * 4)
113 #define PCMD3 __REG(0x40F00080 + 3 * 4)
114 #define PCMD4 __REG(0x40F00080 + 4 * 4)
115 #define PCMD5 __REG(0x40F00080 + 5 * 4)
116 #define PCMD6 __REG(0x40F00080 + 6 * 4)
117 #define PCMD7 __REG(0x40F00080 + 7 * 4)
118 #define PCMD8 __REG(0x40F00080 + 8 * 4)
119 #define PCMD9 __REG(0x40F00080 + 9 * 4)
120 #define PCMD10 __REG(0x40F00080 + 10 * 4)
121 #define PCMD11 __REG(0x40F00080 + 11 * 4)
122 #define PCMD12 __REG(0x40F00080 + 12 * 4)
123 #define PCMD13 __REG(0x40F00080 + 13 * 4)
124 #define PCMD14 __REG(0x40F00080 + 14 * 4)
125 #define PCMD15 __REG(0x40F00080 + 15 * 4)
126 #define PCMD16 __REG(0x40F00080 + 16 * 4)
127 #define PCMD17 __REG(0x40F00080 + 17 * 4)
128 #define PCMD18 __REG(0x40F00080 + 18 * 4)
129 #define PCMD19 __REG(0x40F00080 + 19 * 4)
130 #define PCMD20 __REG(0x40F00080 + 20 * 4)
131 #define PCMD21 __REG(0x40F00080 + 21 * 4)
132 #define PCMD22 __REG(0x40F00080 + 22 * 4)
133 #define PCMD23 __REG(0x40F00080 + 23 * 4)
134 #define PCMD24 __REG(0x40F00080 + 24 * 4)
135 #define PCMD25 __REG(0x40F00080 + 25 * 4)
136 #define PCMD26 __REG(0x40F00080 + 26 * 4)
137 #define PCMD27 __REG(0x40F00080 + 27 * 4)
138 #define PCMD28 __REG(0x40F00080 + 28 * 4)
139 #define PCMD29 __REG(0x40F00080 + 29 * 4)
140 #define PCMD30 __REG(0x40F00080 + 30 * 4)
141 #define PCMD31 __REG(0x40F00080 + 31 * 4)
202 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
203 #define CCSR __REG(0x4130000C) /* Core Clock Status Register */
204 #define CKEN __REG(0x41300004) /* Clock Enable Register */
205 #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */