Lines Matching refs:__REG
58 #define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
59 #define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
60 #define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
61 #define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
87 #define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
88 #define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
89 #define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
90 #define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
95 #define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
96 #define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04)
97 #define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08)
98 #define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c)
99 #define VIC1_INTEN __REG(VIC1_PHYS + 0x10)
100 #define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14)
101 #define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18)
102 #define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
103 #define VIC1_PROTECT __REG(VIC1_PHYS + 0x20)
104 #define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30)
105 #define VIC1_NVADDR __REG(VIC1_PHYS + 0x34)
106 #define VIC1_VAD0 __REG(VIC1_PHYS + 0x100)
107 #define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200)
108 #define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00)
109 #define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04)
110 #define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08)
111 #define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c)
112 #define VIC2_INTEN __REG(VIC2_PHYS + 0x10)
113 #define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14)
114 #define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18)
115 #define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
116 #define VIC2_PROTECT __REG(VIC2_PHYS + 0x20)
117 #define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30)
118 #define VIC2_NVADDR __REG(VIC2_PHYS + 0x34)
119 #define VIC2_VAD0 __REG(VIC2_PHYS + 0x100)
120 #define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200)
126 #define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08)
131 #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
132 #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
133 #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
134 #define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
135 #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
136 #define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
137 #define GPIO_PADD __REG(GPIO_PHYS + 0x10)
138 #define GPIO_PAD __REG(GPIO_PHYS + 0x00)
139 #define GPIO_PCD __REG(GPIO_PHYS + 0x08)
140 #define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
141 #define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
142 #define GPIO_PED __REG(GPIO_PHYS + 0x20)
147 #define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */
148 #define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */
149 #define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */
150 #define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */
151 #define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */
152 #define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */
190 #define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
191 #define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
192 #define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
193 #define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
195 #define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
196 #define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
197 #define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
198 #define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
200 #define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
202 #define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
203 #define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
204 #define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
205 #define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
215 #define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */
216 #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */
217 #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
218 #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
219 #define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
220 #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
221 #define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */