Lines Matching refs:AT91_PMC
19 #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
20 #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
22 #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
39 #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
40 #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
41 #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
43 #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
49 #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
54 #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
58 #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
59 #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
70 #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
102 #define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
108 #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
113 #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
114 #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
115 #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
126 #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
128 #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
131 #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */