Lines Matching refs:divider
122 u32 multiplier, divider, ras_multiplier, ras_divider, tmp;
127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
133 divider = divider * (bpp >> 2);
145 divider = divider * pll->xres & ~7;
151 /* If we don't do this, 32 bits for multiplier & divider won't be
153 while (((multiplier | divider) & 1) == 0) {
155 divider = divider >> 1;
159 tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
172 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
176 dsp_on = ((multiplier * 20 << vshift) + divider) / divider;
179 dsp_on = ((multiplier << vshift) + divider) / divider;
191 dsp_on = dsp_off - (multiplier << vshift) / divider;
196 dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider;
234 /* Set ECP (scaler/overlay clock) divider */
314 /* Set post-divider */
321 /* Set extended post-divider */
328 /* Set feedback divider */