Lines Matching refs:reg_pat
341 (((mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines *
342 mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck) * 0x00000400) /
343 (mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines *
344 mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck));
347 (uint32_t) ((mt9p012_regs.reg_pat[RES_CAPTURE].pll_multiplier *
348 0x00000400) / (mt9p012_regs.reg_pat[RES_PREVIEW].pll_multiplier));
363 return mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines;
365 return mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines;
371 return mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck;
373 return mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck;
378 return mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines;
383 return mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck;
392 mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines - 1;
395 mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines - 1;
418 (mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck *
468 if ((mt9p012_regs.reg_pat[setting].frame_length_lines - 1) < line) {
470 (mt9p012_regs.reg_pat[setting].frame_length_lines - 1);
553 {REG_ROW_SPEED, mt9p012_regs.reg_pat[rt].row_speed},
554 {REG_X_ADDR_START, mt9p012_regs.reg_pat[rt].x_addr_start},
555 {REG_X_ADDR_END, mt9p012_regs.reg_pat[rt].x_addr_end},
556 {REG_Y_ADDR_START, mt9p012_regs.reg_pat[rt].y_addr_start},
557 {REG_Y_ADDR_END, mt9p012_regs.reg_pat[rt].y_addr_end},
558 {REG_READ_MODE, mt9p012_regs.reg_pat[rt].read_mode},
559 {REG_SCALE_M, mt9p012_regs.reg_pat[rt].scale_m},
560 {REG_X_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].x_output_size},
561 {REG_Y_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].y_output_size},
563 {REG_LINE_LENGTH_PCK, mt9p012_regs.reg_pat[rt].line_length_pck},
565 (mt9p012_regs.reg_pat[rt].frame_length_lines *
567 {REG_COARSE_INT_TIME, mt9p012_regs.reg_pat[rt].coarse_int_time},
568 {REG_FINE_INTEGRATION_TIME, mt9p012_regs.reg_pat[rt].fine_int_time},
598 {REG_VT_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_pix_clk_div},
599 {REG_VT_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_sys_clk_div},
600 {REG_PRE_PLL_CLK_DIV, mt9p012_regs.reg_pat[rt].pre_pll_clk_div},
601 {REG_PLL_MULTIPLIER, mt9p012_regs.reg_pat[rt].pll_multiplier},
602 {REG_OP_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].op_pix_clk_div},
603 {REG_OP_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].op_sys_clk_div},
630 {REG_VT_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_pix_clk_div},
631 {REG_VT_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_sys_clk_div},
632 {REG_PRE_PLL_CLK_DIV, mt9p012_regs.reg_pat[rt].pre_pll_clk_div},
633 {REG_PLL_MULTIPLIER, mt9p012_regs.reg_pat[rt].pll_multiplier},
634 {REG_OP_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].op_pix_clk_div},
635 {REG_OP_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].op_sys_clk_div},
663 {REG_ROW_SPEED, mt9p012_regs.reg_pat[rt].row_speed},
664 {REG_X_ADDR_START, mt9p012_regs.reg_pat[rt].x_addr_start},
665 {REG_X_ADDR_END, mt9p012_regs.reg_pat[rt].x_addr_end},
666 {REG_Y_ADDR_START, mt9p012_regs.reg_pat[rt].y_addr_start},
667 {REG_Y_ADDR_END, mt9p012_regs.reg_pat[rt].y_addr_end},
668 {REG_READ_MODE, mt9p012_regs.reg_pat[rt].read_mode},
669 {REG_SCALE_M, mt9p012_regs.reg_pat[rt].scale_m},
670 {REG_X_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].x_output_size},
671 {REG_Y_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].y_output_size},
672 {REG_LINE_LENGTH_PCK, mt9p012_regs.reg_pat[rt].line_length_pck},
674 mt9p012_regs.reg_pat[rt].frame_length_lines},
675 {REG_COARSE_INT_TIME, mt9p012_regs.reg_pat[rt].coarse_int_time},
676 {REG_FINE_INTEGRATION_TIME, mt9p012_regs.reg_pat[rt].fine_int_time},