Lines Matching refs:dma_cntrl
839 uint32_t dma_cntrl;
841 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS);
842 if (!(dma_cntrl & DMA_START_BIT)) {
843 dma_cntrl |= DMA_START_BIT;
845 dma_cntrl);
858 uint32_t dma_cntrl, cnt = 30;
862 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS);
866 if (!dma_cntrl & DMA_START_BIT) {
875 dma_cntrl &= ~DMA_START_BIT;
876 crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1091 uint32_t dma_cntrl;
1093 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1094 if (!(dma_cntrl & DMA_START_BIT)) {
1095 dma_cntrl |= DMA_START_BIT;
1096 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1099 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1100 if (!(dma_cntrl & DMA_START_BIT)) {
1101 dma_cntrl |= DMA_START_BIT;
1102 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1110 uint32_t dma_cntrl = 0, count = 30;
1113 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1114 if ((dma_cntrl & DMA_START_BIT)) {
1115 dma_cntrl &= ~DMA_START_BIT;
1116 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1119 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1120 if ((dma_cntrl & DMA_START_BIT)) {
1121 dma_cntrl &= ~DMA_START_BIT;
1122 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1260 uint32_t dma_cntrl, aspm;
1264 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1265 if (dma_cntrl & DMA_START_BIT) {
1266 dma_cntrl &= ~DMA_START_BIT;
1267 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1270 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1271 if (dma_cntrl & DMA_START_BIT) {
1272 dma_cntrl &= ~DMA_START_BIT;
1273 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);