Lines Matching defs:clk_div
59 u16 clk_div; /* baud rate divider */
435 u16 clk_div = 0;
445 if (unlikely(!chip->clk_div))
446 chip->clk_div = dws->max_freq / chip->speed_hz;
500 /* clk_div doesn't support odd number */
501 clk_div = dws->max_freq / speed;
502 clk_div = (clk_div + 1) & 0xfffe;
505 chip->clk_div = clk_div;
577 * 2. clk_div is changed
580 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
586 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);