Lines Matching refs:up
103 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
109 val = readl(up->port.membase + offset);
111 val = (unsigned int)readb(up->port.membase + offset);
116 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
120 writel(value, up->port.membase + offset);
123 writeb(val, up->port.membase + offset);
140 struct uart_hsu_port *up = file->private_data;
150 "MFD HSU port[%d] regs:\n", up->index);
155 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
157 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
159 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
161 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
163 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
165 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
167 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
169 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
171 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
173 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
282 struct uart_hsu_port *up =
285 up->ier |= UART_IER_MSI;
286 serial_out(up, UART_IER, up->ier);
289 void hsu_dma_tx(struct uart_hsu_port *up)
291 struct circ_buf *xmit = &up->port.state->xmit;
292 struct hsu_dma_buffer *dbuf = &up->txbuf;
296 if (up->dma_tx_on)
303 up->port.icount.tx += dbuf->ofs;
307 chan_writel(up->txc, HSU_CH_CR, 0x0);
309 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
310 dma_sync_single_for_device(up->port.dev,
319 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
320 chan_writel(up->txc, HSU_CH_D0TSR, count);
323 chan_writel(up->txc, HSU_CH_DCR, 0x1
327 up->dma_tx_on = 1;
328 chan_writel(up->txc, HSU_CH_CR, 0x1);
332 uart_write_wakeup(&up->port);
357 struct uart_hsu_port *up =
360 if (up->use_dma) {
361 hsu_dma_tx(up);
362 } else if (!(up->ier & UART_IER_THRI)) {
363 up->ier |= UART_IER_THRI;
364 serial_out(up, UART_IER, up->ier);
370 struct uart_hsu_port *up =
372 struct hsu_dma_chan *txc = up->txc;
374 if (up->use_dma)
376 else if (up->ier & UART_IER_THRI) {
377 up->ier &= ~UART_IER_THRI;
378 serial_out(up, UART_IER, up->ier);
384 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
386 struct hsu_dma_buffer *dbuf = &up->rxbuf;
387 struct hsu_dma_chan *chan = up->rxc;
388 struct uart_port *port = &up->port;
398 * the trail bytes out, push them up and reenable the
429 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
450 struct uart_hsu_port *up =
452 struct hsu_dma_chan *chan = up->rxc;
454 if (up->use_dma)
457 up->ier &= ~UART_IER_RLSI;
458 up->port.read_status_mask &= ~UART_LSR_DR;
459 serial_out(up, UART_IER, up->ier);
463 static inline void receive_chars(struct uart_hsu_port *up, int *status)
465 struct tty_struct *tty = up->port.state->port.tty;
473 ch = serial_in(up, UART_RX);
475 up->port.icount.rx++;
480 dev_warn(up->dev, "We really rush into ERR/BI case"
485 up->port.icount.brk++;
492 if (uart_handle_break(&up->port))
495 up->port.icount.parity++;
497 up->port.icount.frame++;
499 up->port.icount.overrun++;
502 *status &= up->port.read_status_mask;
505 if (up->port.cons &&
506 up->port.cons->index == up->port.line) {
508 *status |= up->lsr_break_flag;
509 up->lsr_break_flag = 0;
520 if (uart_handle_sysrq_char(&up->port, ch))
523 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
525 *status = serial_in(up, UART_LSR);
530 static void transmit_chars(struct uart_hsu_port *up)
532 struct circ_buf *xmit = &up->port.state->xmit;
535 if (up->port.x_char) {
536 serial_out(up, UART_TX, up->port.x_char);
537 up->port.icount.tx++;
538 up->port.x_char = 0;
541 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
542 serial_hsu_stop_tx(&up->port);
547 count = up->port.fifosize / 2;
554 count = up->port.fifosize - 4;
557 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
560 up->port.icount.tx++;
566 uart_write_wakeup(&up->port);
569 serial_hsu_stop_tx(&up->port);
572 static inline void check_modem_status(struct uart_hsu_port *up)
576 status = serial_in(up, UART_MSR);
582 up->port.icount.rng++;
584 up->port.icount.dsr++;
587 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
590 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
592 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
600 struct uart_hsu_port *up = dev_id;
604 if (unlikely(!up->running))
607 spin_lock_irqsave(&up->port.lock, flags);
608 if (up->use_dma) {
609 lsr = serial_in(up, UART_LSR);
612 dev_warn(up->dev,
615 check_modem_status(up);
616 spin_unlock_irqrestore(&up->port.lock, flags);
620 iir = serial_in(up, UART_IIR);
622 spin_unlock_irqrestore(&up->port.lock, flags);
626 lsr = serial_in(up, UART_LSR);
628 receive_chars(up, &lsr);
629 check_modem_status(up);
633 transmit_chars(up);
635 spin_unlock_irqrestore(&up->port.lock, flags);
641 struct uart_hsu_port *up = chan->uport;
645 spin_lock_irqsave(&up->port.lock, flags);
647 if (!up->use_dma || !up->running)
658 hsu_dma_rx(up, int_sts);
663 up->dma_tx_on = 0;
664 hsu_dma_tx(up);
668 spin_unlock_irqrestore(&up->port.lock, flags);
691 struct uart_hsu_port *up =
696 spin_lock_irqsave(&up->port.lock, flags);
697 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
698 spin_unlock_irqrestore(&up->port.lock, flags);
705 struct uart_hsu_port *up =
710 status = serial_in(up, UART_MSR);
726 struct uart_hsu_port *up =
741 mcr |= up->mcr;
743 serial_out(up, UART_MCR, mcr);
748 struct uart_hsu_port *up =
752 spin_lock_irqsave(&up->port.lock, flags);
754 up->lcr |= UART_LCR_SBC;
756 up->lcr &= ~UART_LCR_SBC;
757 serial_out(up, UART_LCR, up->lcr);
758 spin_unlock_irqrestore(&up->port.lock, flags);
770 struct uart_hsu_port *up =
778 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
779 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
781 serial_out(up, UART_FCR, 0);
784 (void) serial_in(up, UART_LSR);
785 (void) serial_in(up, UART_RX);
786 (void) serial_in(up, UART_IIR);
787 (void) serial_in(up, UART_MSR);
790 serial_out(up, UART_LCR, UART_LCR_WLEN8);
792 spin_lock_irqsave(&up->port.lock, flags);
794 up->port.mctrl |= TIOCM_OUT2;
795 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
802 if (!up->use_dma)
803 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
805 up->ier = 0;
806 serial_out(up, UART_IER, up->ier);
808 spin_unlock_irqrestore(&up->port.lock, flags);
811 if (up->use_dma) {
815 up->dma_tx_on = 0;
818 dbuf = &up->rxbuf;
821 up->use_dma = 0;
831 hsu_dma_start_rx_chan(up->rxc, dbuf);
834 dbuf = &up->txbuf;
843 chan_writel(up->txc, HSU_CH_BSR, 32);
844 chan_writel(up->txc, HSU_CH_MOTSR, 4);
850 (void) serial_in(up, UART_LSR);
851 (void) serial_in(up, UART_RX);
852 (void) serial_in(up, UART_IIR);
853 (void) serial_in(up, UART_MSR);
855 up->running = 1;
861 struct uart_hsu_port *up =
865 del_timer_sync(&up->rxc->rx_timer);
868 up->ier = 0;
869 serial_out(up, UART_IER, 0);
870 up->running = 0;
872 spin_lock_irqsave(&up->port.lock, flags);
873 up->port.mctrl &= ~TIOCM_OUT2;
874 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
875 spin_unlock_irqrestore(&up->port.lock, flags);
878 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
879 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
882 serial_out(up, UART_FCR, 0);
889 struct uart_hsu_port *up =
957 if ((up->port.uartclk / quot) < (2400 * 16))
959 else if ((up->port.uartclk / quot) < (230400 * 16))
974 spin_lock_irqsave(&up->port.lock, flags);
979 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
981 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
983 up->port.read_status_mask |= UART_LSR_BI;
986 up->port.ignore_status_mask = 0;
988 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
990 up->port.ignore_status_mask |= UART_LSR_BI;
996 up->port.ignore_status_mask |= UART_LSR_OE;
1001 up->port.ignore_status_mask |= UART_LSR_DR;
1007 up->ier &= ~UART_IER_MSI;
1008 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1009 up->ier |= UART_IER_MSI;
1011 serial_out(up, UART_IER, up->ier);
1014 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1016 up->mcr &= ~UART_MCR_AFE;
1018 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1019 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1020 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1021 serial_out(up, UART_LCR, cval); /* reset DLAB */
1022 serial_out(up, UART_MUL, mul); /* set MUL */
1023 serial_out(up, UART_PS, ps); /* set PS */
1024 up->lcr = cval; /* Save LCR */
1025 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1026 serial_out(up, UART_FCR, fcr);
1027 spin_unlock_irqrestore(&up->port.lock, flags);
1047 struct uart_hsu_port *up =
1049 up->port.type = PORT_MFD;
1062 struct uart_hsu_port *up =
1064 return up->name;
1076 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1080 /* Wait up to 1ms for the character to be sent. */
1082 status = serial_in(up, UART_LSR);
1085 up->lsr_break_flag = UART_LSR_BI;
1092 /* Wait up to 1s for flow control if necessary */
1093 if (up->port.flags & UPF_CONS_FLOW) {
1096 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1103 struct uart_hsu_port *up =
1106 wait_for_xmitr(up);
1107 serial_out(up, UART_TX, ch);
1119 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1125 if (up->port.sysrq)
1128 locked = spin_trylock(&up->port.lock);
1130 spin_lock(&up->port.lock);
1133 ier = serial_in(up, UART_IER);
1134 serial_out(up, UART_IER, 0);
1136 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1142 wait_for_xmitr(up);
1143 serial_out(up, UART_IER, ier);
1146 spin_unlock(&up->port.lock);
1155 struct uart_hsu_port *up;
1164 up = serial_hsu_ports[co->index];
1165 if (!up)
1171 ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1220 struct uart_hsu_port *up;
1224 up = priv;
1225 uart_suspend_port(&serial_hsu_reg, &up->port);
1236 struct uart_hsu_port *up;
1248 up = priv;
1249 uart_resume_port(&serial_hsu_reg, &up->port);
1334 struct uart_hsu_port *up = chan->uport;
1335 struct hsu_dma_buffer *dbuf = &up->rxbuf;
1339 spin_lock_irqsave(&up->port.lock, flags);
1348 hsu_dma_rx(up, 0);
1350 spin_unlock_irqrestore(&up->port.lock, flags);
1436 struct uart_hsu_port *up;
1443 up = priv;
1444 uart_remove_one_port(&serial_hsu_reg, &up->port);