Lines Matching refs:up
236 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
239 if (!ZS_REGS_HELD(up)) {
240 if (ZS_TX_ACTIVE(up)) {
241 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
243 __load_zsregs(channel, up->curregs);
251 static struct tty_struct *ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
259 if (up->port.state != NULL &&
260 up->port.state->port.tty != NULL)
261 tty = up->port.state->port.tty;
279 ch &= up->parity_mask;
283 r1 |= up->tty_break;
287 up->port.icount.rx++;
289 up->tty_break = 0;
292 up->port.icount.brk++;
298 up->port.icount.parity++;
300 up->port.icount.frame++;
302 up->port.icount.overrun++;
303 r1 &= up->port.read_status_mask;
312 if (uart_handle_sysrq_char(&up->port, ch))
316 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
321 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
333 if (up->curregs[R15] & BRKIE) {
334 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
335 if (uart_handle_break(&up->port))
336 up->tty_break = Rx_SYS;
338 up->tty_break = Rx_BRK;
342 if (ZS_WANTS_MODEM_STATUS(up)) {
344 up->port.icount.dsr++;
350 if ((status ^ up->prev_status) ^ DCD)
351 uart_handle_dcd_change(&up->port,
353 if ((status ^ up->prev_status) ^ CTS)
354 uart_handle_cts_change(&up->port,
357 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
360 up->prev_status = status;
363 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
368 if (ZS_IS_CONS(up)) {
384 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
386 if (ZS_REGS_HELD(up)) {
387 __load_zsregs(channel, up->curregs);
388 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
391 if (ZS_TX_STOPPED(up)) {
392 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
396 if (up->port.x_char) {
397 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
398 writeb(up->port.x_char, &channel->data);
402 up->port.icount.tx++;
403 up->port.x_char = 0;
407 if (up->port.state == NULL)
409 xmit = &up->port.state->xmit;
412 if (uart_tx_stopped(&up->port))
415 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
421 up->port.icount.tx++;
424 uart_write_wakeup(&up->port);
436 struct uart_ip22zilog_port *up = dev_id;
438 while (up) {
440 = ZILOG_CHANNEL_FROM_PORT(&up->port);
444 spin_lock(&up->port.lock);
455 tty = ip22zilog_receive_chars(up, channel);
457 ip22zilog_status_handle(up, channel);
459 ip22zilog_transmit_chars(up, channel);
461 spin_unlock(&up->port.lock);
467 up = up->next;
468 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
470 spin_lock(&up->port.lock);
478 tty = ip22zilog_receive_chars(up, channel);
480 ip22zilog_status_handle(up, channel);
482 ip22zilog_transmit_chars(up, channel);
484 spin_unlock(&up->port.lock);
489 up = up->next;
553 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
569 up->curregs[R5] |= set_bits;
570 up->curregs[R5] &= ~clear_bits;
571 write_zsreg(channel, R5, up->curregs[R5]);
577 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
579 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
585 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
589 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
590 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
620 uart_write_wakeup(&up->port);
627 struct uart_ip22zilog_port *up = UART_ZILOG(port);
630 if (ZS_IS_CONS(up))
636 up->curregs[R1] &= ~RxINT_MASK;
637 ip22zilog_maybe_update_regs(up, channel);
643 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
647 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
648 if (new_reg != up->curregs[R15]) {
649 up->curregs[R15] = new_reg;
652 write_zsreg(channel, R15, up->curregs[R15]);
659 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
673 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
674 if (new_reg != up->curregs[R5]) {
675 up->curregs[R5] = new_reg;
678 write_zsreg(channel, R5, up->curregs[R5]);
684 static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
689 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
693 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
701 if (!ZS_IS_CHANNEL_A(up)) {
702 up++;
703 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
709 up->flags |= IP22ZILOG_FLAG_RESET_DONE;
710 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
713 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
717 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
719 __ip22zilog_reset(up);
721 __load_zsregs(channel, up->curregs);
723 write_zsreg(channel, R9, up->curregs[R9]);
724 up->prev_status = readb(&channel->control);
727 up->curregs[R3] |= RxENAB;
728 up->curregs[R5] |= TxENAB;
730 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
731 ip22zilog_maybe_update_regs(up, channel);
736 struct uart_ip22zilog_port *up = UART_ZILOG(port);
739 if (ZS_IS_CONS(up))
743 __ip22zilog_startup(up);
775 struct uart_ip22zilog_port *up = UART_ZILOG(port);
779 if (ZS_IS_CONS(up))
787 up->curregs[R3] &= ~RxENAB;
788 up->curregs[R5] &= ~TxENAB;
791 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
792 up->curregs[R5] &= ~SND_BRK;
793 ip22zilog_maybe_update_regs(up, channel);
802 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
806 up->curregs[R10] = NRZ;
807 up->curregs[R11] = TCBR | RCBR;
810 up->curregs[R4] &= ~XCLK_MASK;
811 up->curregs[R4] |= X16CLK;
812 up->curregs[R12] = brg & 0xff;
813 up->curregs[R13] = (brg >> 8) & 0xff;
814 up->curregs[R14] = BRENAB;
817 up->curregs[3] &= ~RxN_MASK;
818 up->curregs[5] &= ~TxN_MASK;
821 up->curregs[3] |= Rx5;
822 up->curregs[5] |= Tx5;
823 up->parity_mask = 0x1f;
826 up->curregs[3] |= Rx6;
827 up->curregs[5] |= Tx6;
828 up->parity_mask = 0x3f;
831 up->curregs[3] |= Rx7;
832 up->curregs[5] |= Tx7;
833 up->parity_mask = 0x7f;
837 up->curregs[3] |= Rx8;
838 up->curregs[5] |= Tx8;
839 up->parity_mask = 0xff;
842 up->curregs[4] &= ~0x0c;
844 up->curregs[4] |= SB2;
846 up->curregs[4] |= SB1;
848 up->curregs[4] |= PAR_ENAB;
850 up->curregs[4] &= ~PAR_ENAB;
852 up->curregs[4] |= PAR_EVEN;
854 up->curregs[4] &= ~PAR_EVEN;
856 up->port.read_status_mask = Rx_OVR;
858 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
860 up->port.read_status_mask |= BRK_ABRT;
862 up->port.ignore_status_mask = 0;
864 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
866 up->port.ignore_status_mask |= BRK_ABRT;
868 up->port.ignore_status_mask |= Rx_OVR;
872 up->port.ignore_status_mask = 0xff;
880 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
886 spin_lock_irqsave(&up->port.lock, flags);
890 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
892 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
893 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
895 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
897 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
900 spin_unlock_irqrestore(&up->port.lock, flags);
1019 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1022 spin_lock_irqsave(&up->port.lock, flags);
1023 uart_console_write(&up->port, s, count, ip22zilog_put_char);
1025 spin_unlock_irqrestore(&up->port.lock, flags);
1030 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1036 up->flags |= IP22ZILOG_FLAG_IS_CONS;
1040 spin_lock_irqsave(&up->port.lock, flags);
1042 up->curregs[R15] |= BRKIE;
1044 __ip22zilog_startup(up);
1046 spin_unlock_irqrestore(&up->port.lock, flags);
1050 return uart_set_options(&up->port, con, baud, parity, bits, flow);
1080 struct uart_ip22zilog_port *up;
1091 up = &ip22zilog_port_table[0];
1093 up[channel].next = &up[channel - 1];
1094 up[channel].next = NULL;
1100 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1101 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1104 up[(chip * 2) + 0].port.mapbase =
1106 up[(chip * 2) + 1].port.mapbase =
1111 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1112 up[(chip * 2) + 0].port.irq = zilog_irq;
1113 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1114 up[(chip * 2) + 0].port.fifosize = 1;
1115 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1116 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1117 up[(chip * 2) + 0].port.flags = 0;
1118 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1119 up[(chip * 2) + 0].flags = 0;
1122 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1123 up[(chip * 2) + 1].port.irq = zilog_irq;
1124 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1125 up[(chip * 2) + 1].port.fifosize = 1;
1126 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1127 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1128 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1129 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1133 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1137 up->parity_mask = 0xff;
1138 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1139 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1140 up->curregs[R3] = RxENAB | Rx8;
1141 up->curregs[R5] = TxENAB | Tx8;
1142 up->curregs[R9] = NV | MIE;
1143 up->curregs[R10] = NRZ;
1144 up->curregs[R11] = TCBR | RCBR;
1146 up->curregs[R12] = (brg & 0xff);
1147 up->curregs[R13] = (brg >> 8) & 0xff;
1148 up->curregs[R14] = BRENAB;
1170 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1172 uart_add_one_port(&ip22zilog_reg, &up->port);
1191 struct uart_ip22zilog_port *up;
1194 up = &ip22zilog_port_table[i];
1196 uart_remove_one_port(&ip22zilog_reg, &up->port);
1200 up = &ip22zilog_port_table[0];
1202 if (up[(i * 2) + 0].port.mapbase) {
1203 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1204 up[(i * 2) + 0].port.mapbase = 0;
1206 if (up[(i * 2) + 1].port.mapbase) {
1207 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1208 up[(i * 2) + 1].port.mapbase = 0;