Lines Matching refs:qbase
81 int qbase = priv->qbase;
84 x = inb(qbase + 0xd);
86 outb(3, qbase + 3); /* reset SCSI */
87 outb(2, qbase + 3); /* reset chip */
99 int qbase = priv->qbase;
105 if (reqlen >= 128 && (inb(qbase + 8) & 2)) { /* full */
106 insl(qbase + 4, request, 32);
111 if ((j = inb(qbase + 8)) & 4)
113 insl(qbase + 4, request, 21);
117 if (reqlen >= 44 && (inb(qbase + 8) & 8)) { /* 1/3 */
118 insl(qbase + 4, request, 11);
130 while (reqlen && !((j = inb(qbase + 8)) & 0x10))
132 *request++ = inb(qbase + 4);
136 j = inb(qbase + 8);
142 if (reqlen >= 128 && inb(qbase + 8) & 0x10) { /* empty */
143 outsl(qbase + 4, request, 32);
148 if (!((j = inb(qbase + 8)) & 8)) {
149 outsl(qbase + 4, request, 21);
153 if (reqlen >= 40 && !(inb(qbase + 8) & 4)) { /* 2/3 */
154 outsl(qbase + 4, request, 10);
164 while (reqlen && !((j = inb(qbase + 8)) & 2))
166 outb(*request++, qbase + 4);
170 j = inb(qbase + 8);
174 return inb(qbase + 8) & 0xc0;
184 int qbase = priv->qbase;
190 !((k = inb(qbase + 4)) & 0xe0)) {
215 int qbase = priv->qbase;
224 inb(qbase + 5); /* clear interrupts */
225 if (inb(qbase + 5)) /* if still interrupting */
226 outb(2, qbase + 3); /* reset chip */
227 else if (inb(qbase + 7) & 0x1f)
228 outb(1, qbase + 3); /* clear fifo */
229 while (inb(qbase + 5)); /* clear ints */
231 outb(1, qbase + 8); /* set for PIO pseudo DMA */
232 outb(0, qbase + 0xb); /* disable ints */
233 inb(qbase + 8); /* clear int bits */
235 outb(0x40, qbase + 0xb); /* enable features */
238 outb(qlcfgc, qbase + 0xc);
240 outb(0x40 | qlcfg8 | priv->qinitid, qbase + 8);
241 outb(qlcfg7, qbase + 7);
242 outb(qlcfg6, qbase + 6);
243 /**/ outb(qlcfg5, qbase + 5); /* select timer */
244 outb(qlcfg9 & 7, qbase + 9); /* prescaler */
245 /* outb(0x99, qbase + 5); */
246 outb(scmd_id(cmd), qbase + 4);
249 outb(cmd->cmnd[i], qbase + 2);
252 outb(0x41, qbase + 3); /* select and send command */
270 int qbase = priv->qbase;
274 j = inb(qbase + 6);
275 i = inb(qbase + 5);
279 i |= inb(qbase + 5); /* the 0x10 bit can be set after the 0x08 */
285 j &= 7; /* j = inb( qbase + 7 ) >> 5; */
294 j, i, inb(qbase + 7) & 0x1f);
299 if (inb(qbase + 7) & 0x1f) /* if some bytes in fifo */
300 outb(1, qbase + 3); /* clear fifo */
304 if (reqlen && !((phase = inb(qbase + 4)) & 6)) { /* data phase */
307 outb(reqlen, qbase); /* low-mid xfer cnt */
308 outb(reqlen >> 8, qbase + 1); /* low-mid xfer cnt */
309 outb(reqlen >> 16, qbase + 0xe); /* high xfer cnt */
310 outb(0x90, qbase + 3); /* command do xfer */
332 k = inb(qbase + 5); /* should be 0x10, bus service */
342 !(inb(qbase + 4) & 6))
350 while (inb(qbase + 5))
356 outb(0x11, qbase + 3); /* get status and message */
359 i = inb(qbase + 5); /* get chip irq stat */
360 j = inb(qbase + 7) & 0x1f; /* and bytes rec'd */
361 status = inb(qbase + 2);
362 message = inb(qbase + 2);
372 outb(0x12, qbase + 3); /* done, disconnect */
381 i = inb(qbase + 5); /* should be bus service */
385 i |= inb(qbase + 5);
404 int qbase = priv->qbase;
407 if (!(inb(qbase + 4) & 0x80)) /* false alarm? */
413 while (i-- && inb(qbase + 5)); /* maybe also ql_zap() */
521 int qlogicfas408_get_chip_type(int qbase, int int_type)
524 return inb(qbase + 0xe) & 0xf8;
531 void qlogicfas408_setup(int qbase, int id, int int_type)
533 outb(1, qbase + 8); /* set for PIO pseudo DMA */
535 outb(0x40 | qlcfg8 | id, qbase + 8); /* (ini) bus id, disable scsi rst */
536 outb(qlcfg5, qbase + 5); /* select timer */
537 outb(qlcfg9, qbase + 9); /* prescaler */
540 outb(3, qbase + 3);
543 while (inb(qbase + 0xf) & 4)
554 int qlogicfas408_detect(int qbase, int int_type)
557 return (((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7) &&
558 ((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7));
567 int qbase = priv->qbase;
571 outb(0, qbase + 0xb); /* disable ints */