Lines Matching refs:mvi
43 static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
45 void __iomem *regs = mvi->regs;
50 static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
52 void __iomem *regs = mvi->regs;
57 static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
59 void __iomem *regs = mvi->regs;
64 static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
66 void __iomem *regs = mvi->regs;
73 static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
76 void __iomem *regs = mvi->regs + off;
77 void __iomem *regs2 = mvi->regs + off2;
82 static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
85 void __iomem *regs = mvi->regs + off;
86 void __iomem *regs2 = mvi->regs + off2;
93 static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
95 return mvs_read_port(mvi, MVS_P0_CFG_DATA,
99 static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
102 mvs_write_port(mvi, MVS_P0_CFG_DATA,
106 static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
109 mvs_write_port(mvi, MVS_P0_CFG_ADDR,
114 static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
116 return mvs_read_port(mvi, MVS_P0_VSR_DATA,
120 static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
123 mvs_write_port(mvi, MVS_P0_VSR_DATA,
127 static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
130 mvs_write_port(mvi, MVS_P0_VSR_ADDR,
135 static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
137 return mvs_read_port(mvi, MVS_P0_INT_STAT,
141 static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
144 mvs_write_port(mvi, MVS_P0_INT_STAT,
148 static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
150 return mvs_read_port(mvi, MVS_P0_INT_MASK,
155 static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
158 mvs_write_port(mvi, MVS_P0_INT_MASK,
162 static inline void __devinit mvs_phy_hacks(struct mvs_info *mvi)
166 tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
169 mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
172 mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
175 tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
178 mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
180 mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
183 mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
185 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
188 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
190 tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
193 mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
196 static inline void mvs_int_sata(struct mvs_info *mvi)
199 void __iomem *regs = mvi->regs;
203 MVS_CHIP_DISP->clear_active_cmds(mvi);
206 static inline void mvs_int_full(struct mvs_info *mvi)
208 void __iomem *regs = mvi->regs;
213 mvs_int_rx(mvi, false);
215 for (i = 0; i < mvi->chip->n_phy; i++) {
218 mvs_int_port(mvi, i, tmp);
222 mvs_int_sata(mvi);
227 static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
229 void __iomem *regs = mvi->regs;
233 static inline u32 mvs_rx_update(struct mvs_info *mvi)
235 void __iomem *regs = mvi->regs;
249 static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
257 if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
260 pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
264 dev_printk(KERN_INFO, mvi->dev,