Lines Matching refs:iwl_write_prph
160 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
161 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
162 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
163 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
176 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
177 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
178 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
182 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
200 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
226 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
227 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
228 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
233 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
312 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
468 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
488 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
533 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
548 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
554 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
573 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1710 iwl_write_prph(priv,