Lines Matching defs:mem_crb
1474 void __iomem *mem_crb;
1483 mem_crb = pci_base_offset(adapter,
1494 mem_crb = pci_base_offset(adapter,
1518 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1519 writel(off_hi, (mem_crb + addr_hi));
1520 writel(data & 0xffffffff, (mem_crb + data_lo));
1521 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1522 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1524 (mem_crb + TEST_AGT_CTRL));
1527 temp = readl((mem_crb + TEST_AGT_CTRL));
1552 void __iomem *mem_crb;
1561 mem_crb = pci_base_offset(adapter,
1572 mem_crb = pci_base_offset(adapter,
1596 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1597 writel(off_hi, (mem_crb + addr_hi));
1598 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1599 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1602 temp = readl(mem_crb + TEST_AGT_CTRL);
1614 temp = readl(mem_crb + data_hi);
1616 val |= readl(mem_crb + data_lo);
1633 void __iomem *mem_crb;
1642 mem_crb = netxen_get_ioaddr(adapter,
1648 mem_crb = netxen_get_ioaddr(adapter,
1663 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1664 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1667 mem_crb + MIU_TEST_AGT_WRDATA_LO);
1669 mem_crb + MIU_TEST_AGT_WRDATA_HI);
1671 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1673 (mem_crb + TEST_AGT_CTRL));
1676 temp = readl(mem_crb + TEST_AGT_CTRL);
1701 void __iomem *mem_crb;
1710 mem_crb = netxen_get_ioaddr(adapter,
1716 mem_crb = netxen_get_ioaddr(adapter,
1733 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1734 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1735 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1736 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1739 temp = readl(mem_crb + TEST_AGT_CTRL);
1750 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32;
1751 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);