Lines Matching defs:jme
42 #include "jme.h"
59 struct jme_adapter *jme = netdev_priv(netdev);
63 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 val = jread32(jme, JME_SMI);
76 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
90 struct jme_adapter *jme = netdev_priv(netdev);
93 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
105 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
109 jme_reset_phy_processor(struct jme_adapter *jme)
113 jme_mdio_write(jme->dev,
114 jme->mii_if.phy_id,
118 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
124 val = jme_mdio_read(jme->dev,
125 jme->mii_if.phy_id,
128 jme_mdio_write(jme->dev,
129 jme->mii_if.phy_id,
134 jme_setup_wakeup_frame(struct jme_adapter *jme,
142 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
144 jwrite32(jme, JME_WFODP, crc);
151 jwrite32(jme, JME_WFOI,
155 jwrite32(jme, JME_WFODP, mask[i]);
161 jme_reset_mac_processor(struct jme_adapter *jme)
168 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
170 jwrite32(jme, JME_GHC, jme->reg_ghc);
172 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
173 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
174 jwrite32(jme, JME_RXQDC, 0x00000000);
175 jwrite32(jme, JME_RXNDA, 0x00000000);
176 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
177 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
178 jwrite32(jme, JME_TXQDC, 0x00000000);
179 jwrite32(jme, JME_TXNDA, 0x00000000);
181 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
182 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
184 jme_setup_wakeup_frame(jme, mask, crc, i);
185 if (jme->fpgaver)
189 jwrite32(jme, JME_GPREG0, gpreg0);
190 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194 jme_reset_ghc_speed(struct jme_adapter *jme)
196 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
197 jwrite32(jme, JME_GHC, jme->reg_ghc);
201 jme_clear_pm(struct jme_adapter *jme)
203 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
204 pci_set_power_state(jme->pdev, PCI_D0);
205 pci_enable_wake(jme->pdev, PCI_D0, false);
209 jme_reload_eeprom(struct jme_adapter *jme)
214 val = jread32(jme, JME_SMBCSR);
218 jwrite32(jme, JME_SMBCSR, val);
220 jwrite32(jme, JME_SMBCSR, val);
225 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
230 jeprintk(jme->pdev, "eeprom reload timeout\n");
241 struct jme_adapter *jme = netdev_priv(netdev);
245 spin_lock_bh(&jme->macaddr_lock);
246 val = jread32(jme, JME_RXUMA_LO);
251 val = jread32(jme, JME_RXUMA_HI);
255 spin_unlock_bh(&jme->macaddr_lock);
259 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 jwrite32(jme, JME_PCCRX0,
268 jwrite32(jme, JME_PCCRX0,
273 jwrite32(jme, JME_PCCRX0,
278 jwrite32(jme, JME_PCCRX0,
287 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
288 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
292 jme_start_irq(struct jme_adapter *jme)
294 register struct dynpcc_info *dpi = &(jme->dpi);
296 jme_set_rx_pcc(jme, PCC_P1);
301 jwrite32(jme, JME_PCCTX,
310 jwrite32(jme, JME_IENS, INTR_ENABLE);
314 jme_stop_irq(struct jme_adapter *jme)
319 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 jme_linkstat_from_phy(struct jme_adapter *jme)
327 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
328 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
336 jme_set_phyfifoa(struct jme_adapter *jme)
338 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342 jme_set_phyfifob(struct jme_adapter *jme)
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
350 struct jme_adapter *jme = netdev_priv(netdev);
357 if (jme->fpgaver)
358 phylink = jme_linkstat_from_phy(jme);
360 phylink = jread32(jme, JME_PHY_LINK);
370 bmcr = jme_mdio_read(jme->dev,
371 jme->mii_if.phy_id,
394 if (jme->fpgaver)
395 phylink = jme_linkstat_from_phy(jme);
397 phylink = jread32(jme, JME_PHY_LINK);
400 jeprintk(jme->pdev,
406 if (jme->phylink == phylink) {
413 jme->phylink = phylink;
415 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
439 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
446 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
453 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
458 jme_set_phyfifoa(jme);
462 jme_set_phyfifob(jme);
466 jme_set_phyfifoa(jme);
473 jwrite32(jme, JME_GPREG1, gpreg1);
474 jwrite32(jme, JME_GHC, ghc);
475 jme->reg_ghc = ghc;
483 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
489 netif_info(jme, link, jme->dev, "Link is down.\n");
490 jme->phylink = 0;
499 jme_setup_tx_resources(struct jme_adapter *jme)
501 struct jme_ring *txring = &(jme->txring[0]);
503 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
504 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
519 atomic_set(&txring->nr_free, jme->tx_ring_size);
522 jme->tx_ring_size, GFP_ATOMIC);
529 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
531 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
536 dma_free_coherent(&(jme->pdev->dev),
537 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
551 jme_free_tx_resources(struct jme_adapter *jme)
554 struct jme_ring *txring = &(jme->txring[0]);
559 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
573 dma_free_coherent(&(jme->pdev->dev),
574 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
590 jme_enable_tx_engine(struct jme_adapter *jme)
595 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
601 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
602 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
603 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
608 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
614 jwrite32(jme, JME_TXCS, jme->reg_txcs |
621 jme_restart_tx_engine(struct jme_adapter *jme)
626 jwrite32(jme, JME_TXCS, jme->reg_txcs |
632 jme_disable_tx_engine(struct jme_adapter *jme)
640 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
643 val = jread32(jme, JME_TXCS);
646 val = jread32(jme, JME_TXCS);
651 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
655 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
657 struct jme_ring *rxring = &(jme->rxring[0]);
669 if (jme->dev->features & NETIF_F_HIGHDMA)
676 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
678 struct jme_ring *rxring = &(jme->rxring[0]);
682 skb = netdev_alloc_skb(jme->dev,
683 jme->dev->mtu + RX_EXTRA_LEN);
689 rxbi->mapping = pci_map_page(jme->pdev,
699 jme_free_rx_buf(struct jme_adapter *jme, int i)
701 struct jme_ring *rxring = &(jme->rxring[0]);
706 pci_unmap_page(jme->pdev,
718 jme_free_rx_resources(struct jme_adapter *jme)
721 struct jme_ring *rxring = &(jme->rxring[0]);
725 for (i = 0 ; i < jme->rx_ring_size ; ++i)
726 jme_free_rx_buf(jme, i);
730 dma_free_coherent(&(jme->pdev->dev),
731 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
745 jme_setup_rx_resources(struct jme_adapter *jme)
748 struct jme_ring *rxring = &(jme->rxring[0]);
750 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
751 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
767 jme->rx_ring_size, GFP_ATOMIC);
775 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
776 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
777 if (unlikely(jme_make_new_rx_buf(jme, i))) {
778 jme_free_rx_resources(jme);
782 jme_set_clean_rxdesc(jme, i);
788 dma_free_coherent(&(jme->pdev->dev),
789 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
802 jme_enable_rx_engine(struct jme_adapter *jme)
807 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
814 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
815 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
816 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
821 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
826 jme_set_multi(jme->dev);
832 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
839 jme_restart_rx_engine(struct jme_adapter *jme)
844 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
851 jme_disable_rx_engine(struct jme_adapter *jme)
859 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
862 val = jread32(jme, JME_RXCS);
865 val = jread32(jme, JME_RXCS);
870 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
875 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
883 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
890 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
896 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
904 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
906 struct jme_ring *rxring = &(jme->rxring[0]);
916 pci_dma_sync_single_for_cpu(jme->pdev,
921 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
922 pci_dma_sync_single_for_device(jme->pdev,
927 ++(NET_STAT(jme).rx_dropped);
934 skb->protocol = eth_type_trans(skb, jme->dev);
936 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
942 if (jme->vlgrp) {
943 jme->jme_vlan_rx(skb, jme->vlgrp,
945 NET_STAT(jme).rx_bytes += 4;
950 jme->jme_rx(skb);
955 ++(NET_STAT(jme).multicast);
957 NET_STAT(jme).rx_bytes += framesize;
958 ++(NET_STAT(jme).rx_packets);
961 jme_set_clean_rxdesc(jme, idx);
966 jme_process_receive(struct jme_adapter *jme, int limit)
968 struct jme_ring *rxring = &(jme->rxring[0]);
970 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
972 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
975 if (unlikely(atomic_read(&jme->link_changing) != 1))
978 if (unlikely(!netif_carrier_ok(jme->dev)))
997 ++(NET_STAT(jme).rx_crc_errors);
999 ++(NET_STAT(jme).rx_fifo_errors);
1001 ++(NET_STAT(jme).rx_errors);
1007 jme_set_clean_rxdesc(jme, j);
1012 jme_alloc_and_feed_skb(jme, i);
1022 atomic_inc(&jme->rx_cleaning);
1046 jme_dynamic_pcc(struct jme_adapter *jme)
1048 register struct dynpcc_info *dpi = &(jme->dpi);
1050 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1052 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1060 tasklet_schedule(&jme->rxclean_task);
1061 jme_set_rx_pcc(jme, dpi->attempt);
1068 jme_start_pcc_timer(struct jme_adapter *jme)
1070 struct dynpcc_info *dpi = &(jme->dpi);
1071 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1072 dpi->last_pkts = NET_STAT(jme).rx_packets;
1074 jwrite32(jme, JME_TMCSR,
1079 jme_stop_pcc_timer(struct jme_adapter *jme)
1081 jwrite32(jme, JME_TMCSR, 0);
1085 jme_shutdown_nic(struct jme_adapter *jme)
1089 phylink = jme_linkstat_from_phy(jme);
1095 jme_stop_irq(jme);
1096 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1103 struct jme_adapter *jme = (struct jme_adapter *)arg;
1104 struct net_device *netdev = jme->dev;
1106 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1107 jme_shutdown_nic(jme);
1112 (atomic_read(&jme->link_changing) != 1)
1114 jme_stop_pcc_timer(jme);
1118 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1119 jme_dynamic_pcc(jme);
1121 jme_start_pcc_timer(jme);
1125 jme_polling_mode(struct jme_adapter *jme)
1127 jme_set_rx_pcc(jme, PCC_OFF);
1131 jme_interrupt_mode(struct jme_adapter *jme)
1133 jme_set_rx_pcc(jme, PCC_P1);
1137 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1140 apmc = jread32(jme, JME_APMC);
1145 jme_start_shutdown_timer(struct jme_adapter *jme)
1149 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1152 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1155 jwrite32f(jme, JME_APMC, apmc);
1157 jwrite32f(jme, JME_TIMER2, 0);
1158 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1159 jwrite32(jme, JME_TMCSR,
1164 jme_stop_shutdown_timer(struct jme_adapter *jme)
1168 jwrite32f(jme, JME_TMCSR, 0);
1169 jwrite32f(jme, JME_TIMER2, 0);
1170 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172 apmc = jread32(jme, JME_APMC);
1174 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1176 jwrite32f(jme, JME_APMC, apmc);
1182 struct jme_adapter *jme = (struct jme_adapter *)arg;
1183 struct net_device *netdev = jme->dev;
1186 while (!atomic_dec_and_test(&jme->link_changing)) {
1187 atomic_inc(&jme->link_changing);
1188 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
1189 while (atomic_read(&jme->link_changing) != 1)
1190 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
1193 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1196 jme->old_mtu = netdev->mtu;
1198 if (jme_pseudo_hotplug_enabled(jme))
1199 jme_stop_shutdown_timer(jme);
1201 jme_stop_pcc_timer(jme);
1202 tasklet_disable(&jme->txclean_task);
1203 tasklet_disable(&jme->rxclean_task);
1204 tasklet_disable(&jme->rxempty_task);
1207 jme_reset_ghc_speed(jme);
1208 jme_disable_rx_engine(jme);
1209 jme_disable_tx_engine(jme);
1210 jme_reset_mac_processor(jme);
1211 jme_free_rx_resources(jme);
1212 jme_free_tx_resources(jme);
1214 if (test_bit(JME_FLAG_POLL, &jme->flags))
1215 jme_polling_mode(jme);
1222 rc = jme_setup_rx_resources(jme);
1224 jeprintk(jme->pdev, "Allocating resources for RX error"
1229 rc = jme_setup_tx_resources(jme);
1231 jeprintk(jme->pdev, "Allocating resources for TX error"
1236 jme_enable_rx_engine(jme);
1237 jme_enable_tx_engine(jme);
1241 if (test_bit(JME_FLAG_POLL, &jme->flags))
1242 jme_interrupt_mode(jme);
1244 jme_start_pcc_timer(jme);
1245 } else if (jme_pseudo_hotplug_enabled(jme)) {
1246 jme_start_shutdown_timer(jme);
1252 jme_free_rx_resources(jme);
1254 tasklet_enable(&jme->txclean_task);
1255 tasklet_hi_enable(&jme->rxclean_task);
1256 tasklet_hi_enable(&jme->rxempty_task);
1258 atomic_inc(&jme->link_changing);
1264 struct jme_adapter *jme = (struct jme_adapter *)arg;
1265 struct dynpcc_info *dpi = &(jme->dpi);
1267 jme_process_receive(jme, jme->rx_ring_size);
1275 struct jme_adapter *jme = jme_napi_priv(holder);
1278 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1280 while (atomic_read(&jme->rx_empty) > 0) {
1281 atomic_dec(&jme->rx_empty);
1282 ++(NET_STAT(jme).rx_dropped);
1283 jme_restart_rx_engine(jme);
1285 atomic_inc(&jme->rx_empty);
1289 jme_interrupt_mode(jme);
1299 struct jme_adapter *jme = (struct jme_adapter *)arg;
1301 if (unlikely(atomic_read(&jme->link_changing) != 1))
1304 if (unlikely(!netif_carrier_ok(jme->dev)))
1307 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1311 while (atomic_read(&jme->rx_empty) > 0) {
1312 atomic_dec(&jme->rx_empty);
1313 ++(NET_STAT(jme).rx_dropped);
1314 jme_restart_rx_engine(jme);
1316 atomic_inc(&jme->rx_empty);
1320 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1322 struct jme_ring *txring = &(jme->txring[0]);
1325 if (unlikely(netif_queue_stopped(jme->dev) &&
1326 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1327 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
1328 netif_wake_queue(jme->dev);
1336 struct jme_adapter *jme = (struct jme_adapter *)arg;
1337 struct jme_ring *txring = &(jme->txring[0]);
1342 tx_dbg(jme, "Into txclean.\n");
1344 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1347 if (unlikely(atomic_read(&jme->link_changing) != 1))
1350 if (unlikely(!netif_carrier_ok(jme->dev)))
1353 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1354 mask = jme->tx_ring_mask;
1363 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1372 pci_unmap_page(jme->pdev,
1386 ++(NET_STAT(jme).tx_carrier_errors);
1388 ++(NET_STAT(jme).tx_packets);
1389 NET_STAT(jme).tx_bytes += ctxbi->len;
1405 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1409 jme_wake_queue_if_stopped(jme);
1412 atomic_inc(&jme->tx_cleaning);
1416 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1421 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1428 jwrite32(jme, JME_IEVE, intrstat);
1429 tasklet_schedule(&jme->linkch_task);
1434 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1435 tasklet_schedule(&jme->pcc_task);
1439 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1440 tasklet_schedule(&jme->txclean_task);
1444 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1450 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1452 atomic_inc(&jme->rx_empty);
1455 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1456 jme_polling_mode(jme);
1457 JME_RX_SCHEDULE(jme);
1462 atomic_inc(&jme->rx_empty);
1463 tasklet_hi_schedule(&jme->rxempty_task);
1465 tasklet_hi_schedule(&jme->rxclean_task);
1473 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1480 struct jme_adapter *jme = netdev_priv(netdev);
1483 intrstat = jread32(jme, JME_IEVE);
1497 jme_intr_msi(jme, intrstat);
1506 struct jme_adapter *jme = netdev_priv(netdev);
1509 intrstat = jread32(jme, JME_IEVE);
1511 jme_intr_msi(jme, intrstat);
1517 jme_reset_link(struct jme_adapter *jme)
1519 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1523 jme_restart_an(struct jme_adapter *jme)
1527 spin_lock_bh(&jme->phy_lock);
1528 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1530 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1531 spin_unlock_bh(&jme->phy_lock);
1535 jme_request_irq(struct jme_adapter *jme)
1538 struct net_device *netdev = jme->dev;
1542 if (!pci_enable_msi(jme->pdev)) {
1543 set_bit(JME_FLAG_MSI, &jme->flags);
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1551 jeprintk(jme->pdev,
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev);
1558 clear_bit(JME_FLAG_MSI, &jme->flags);
1561 netdev->irq = jme->pdev->irq;
1568 jme_free_irq(struct jme_adapter *jme)
1570 free_irq(jme->pdev->irq, jme->dev);
1571 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1572 pci_disable_msi(jme->pdev);
1573 clear_bit(JME_FLAG_MSI, &jme->flags);
1574 jme->dev->irq = jme->pdev->irq;
1579 jme_phy_on(struct jme_adapter *jme)
1583 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1585 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1591 struct jme_adapter *jme = netdev_priv(netdev);
1594 jme_clear_pm(jme);
1595 JME_NAPI_ENABLE(jme);
1597 tasklet_enable(&jme->linkch_task);
1598 tasklet_enable(&jme->txclean_task);
1599 tasklet_hi_enable(&jme->rxclean_task);
1600 tasklet_hi_enable(&jme->rxempty_task);
1602 rc = jme_request_irq(jme);
1606 jme_start_irq(jme);
1608 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1609 jme_phy_on(jme);
1610 jme_set_settings(netdev, &jme->old_ecmd);
1612 jme_reset_phy_processor(jme);
1615 jme_reset_link(jme);
1627 jme_set_100m_half(struct jme_adapter *jme)
1631 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1637 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1639 if (jme->fpgaver)
1640 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1642 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1647 jme_wait_link(struct jme_adapter *jme)
1652 phylink = jme_linkstat_from_phy(jme);
1655 phylink = jme_linkstat_from_phy(jme);
1661 jme_phy_off(struct jme_adapter *jme)
1663 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1669 struct jme_adapter *jme = netdev_priv(netdev);
1674 jme_stop_irq(jme);
1675 jme_free_irq(jme);
1677 JME_NAPI_DISABLE(jme);
1679 tasklet_disable(&jme->linkch_task);
1680 tasklet_disable(&jme->txclean_task);
1681 tasklet_disable(&jme->rxclean_task);
1682 tasklet_disable(&jme->rxempty_task);
1684 jme_reset_ghc_speed(jme);
1685 jme_disable_rx_engine(jme);
1686 jme_disable_tx_engine(jme);
1687 jme_reset_mac_processor(jme);
1688 jme_free_rx_resources(jme);
1689 jme_free_tx_resources(jme);
1690 jme->phylink = 0;
1691 jme_phy_off(jme);
1697 jme_alloc_txdesc(struct jme_adapter *jme,
1700 struct jme_ring *txring = &(jme->txring[0]);
1701 int idx, nr_alloc, mask = jme->tx_ring_mask;
1752 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1754 struct jme_ring *txring = &(jme->txring[0]);
1757 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1759 int mask = jme->tx_ring_mask;
1768 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1775 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1781 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1824 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1849 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
1865 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1867 struct jme_ring *txring = &(jme->txring[0]);
1893 jme_tx_csum(jme, skb, &flags);
1895 jme_map_tx_skb(jme, skb, idx);
1913 jme_stop_queue_if_full(struct jme_adapter *jme)
1915 struct jme_ring *txring = &(jme->txring[0]);
1923 netif_stop_queue(jme->dev);
1924 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
1927 >= (jme->tx_wake_threshold)) {
1928 netif_wake_queue(jme->dev);
1929 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
1936 netif_stop_queue(jme->dev);
1937 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1948 struct jme_adapter *jme = netdev_priv(netdev);
1951 if (unlikely(jme_expand_header(jme, skb))) {
1952 ++(NET_STAT(jme).tx_dropped);
1956 idx = jme_alloc_txdesc(jme, skb);
1960 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
1965 jme_fill_tx_desc(jme, skb, idx);
1967 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1972 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1975 jme_stop_queue_if_full(jme);
1983 struct jme_adapter *jme = netdev_priv(netdev);
1990 spin_lock_bh(&jme->macaddr_lock);
1997 jwrite32(jme, JME_RXUMA_LO, val);
2000 jwrite32(jme, JME_RXUMA_HI, val);
2001 spin_unlock_bh(&jme->macaddr_lock);
2009 struct jme_adapter *jme = netdev_priv(netdev);
2012 spin_lock_bh(&jme->rxmcs_lock);
2014 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2017 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2019 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2024 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2030 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2031 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2035 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2037 spin_unlock_bh(&jme->rxmcs_lock);
2043 struct jme_adapter *jme = netdev_priv(netdev);
2045 if (new_mtu == jme->old_mtu)
2053 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2054 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2055 jme_restart_rx_engine(jme);
2057 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2058 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2059 jme_restart_rx_engine(jme);
2067 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2069 if (test_bit(JME_FLAG_TSO, &jme->flags))
2074 jme_reset_link(jme);
2082 struct jme_adapter *jme = netdev_priv(netdev);
2084 jme->phylink = 0;
2085 jme_reset_phy_processor(jme);
2086 if (test_bit(JME_FLAG_SSET, &jme->flags))
2087 jme_set_settings(netdev, &jme->old_ecmd);
2092 jme_reset_link(jme);
2095 static inline void jme_pause_rx(struct jme_adapter *jme)
2097 atomic_dec(&jme->link_changing);
2099 jme_set_rx_pcc(jme, PCC_OFF);
2100 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2101 JME_NAPI_DISABLE(jme);
2103 tasklet_disable(&jme->rxclean_task);
2104 tasklet_disable(&jme->rxempty_task);
2108 static inline void jme_resume_rx(struct jme_adapter *jme)
2110 struct dynpcc_info *dpi = &(jme->dpi);
2112 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2113 JME_NAPI_ENABLE(jme);
2115 tasklet_hi_enable(&jme->rxclean_task);
2116 tasklet_hi_enable(&jme->rxempty_task);
2121 jme_set_rx_pcc(jme, PCC_P1);
2123 atomic_inc(&jme->link_changing);
2129 struct jme_adapter *jme = netdev_priv(netdev);
2131 jme_pause_rx(jme);
2132 jme->vlgrp = grp;
2133 jme_resume_rx(jme);
2140 struct jme_adapter *jme = netdev_priv(netdev);
2144 strcpy(info->bus_info, pci_name(jme->pdev));
2154 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2159 p[i >> 2] = jread32(jme, reg + i);
2163 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2169 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2175 struct jme_adapter *jme = netdev_priv(netdev);
2181 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2184 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2187 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2190 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2193 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2199 struct jme_adapter *jme = netdev_priv(netdev);
2204 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2213 switch (jme->dpi.cur) {
2236 struct jme_adapter *jme = netdev_priv(netdev);
2237 struct dynpcc_info *dpi = &(jme->dpi);
2243 test_bit(JME_FLAG_POLL, &jme->flags)) {
2244 clear_bit(JME_FLAG_POLL, &jme->flags);
2245 jme->jme_rx = netif_rx;
2246 jme->jme_vlan_rx = vlan_hwaccel_rx;
2250 jme_set_rx_pcc(jme, PCC_P1);
2251 jme_interrupt_mode(jme);
2253 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2254 set_bit(JME_FLAG_POLL, &jme->flags);
2255 jme->jme_rx = netif_receive_skb;
2256 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2257 jme_interrupt_mode(jme);
2267 struct jme_adapter *jme = netdev_priv(netdev);
2270 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2271 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2273 spin_lock_bh(&jme->phy_lock);
2274 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2275 spin_unlock_bh(&jme->phy_lock);
2285 struct jme_adapter *jme = netdev_priv(netdev);
2288 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2292 jme->reg_txpfc |= TXPFC_PF_EN;
2294 jme->reg_txpfc &= ~TXPFC_PF_EN;
2296 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2299 spin_lock_bh(&jme->rxmcs_lock);
2300 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2304 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2306 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2308 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2310 spin_unlock_bh(&jme->rxmcs_lock);
2312 spin_lock_bh(&jme->phy_lock);
2313 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2322 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2325 spin_unlock_bh(&jme->phy_lock);
2334 struct jme_adapter *jme = netdev_priv(netdev);
2340 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2343 if (jme->reg_pmcs & PMCS_MFEN)
2352 struct jme_adapter *jme = netdev_priv(netdev);
2361 jme->reg_pmcs = 0;
2364 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2367 jme->reg_pmcs |= PMCS_MFEN;
2369 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2378 struct jme_adapter *jme = netdev_priv(netdev);
2381 spin_lock_bh(&jme->phy_lock);
2382 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2383 spin_unlock_bh(&jme->phy_lock);
2391 struct jme_adapter *jme = netdev_priv(netdev);
2397 if (jme->mii_if.force_media &&
2399 (jme->mii_if.full_duplex != ecmd->duplex))
2402 spin_lock_bh(&jme->phy_lock);
2403 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2404 spin_unlock_bh(&jme->phy_lock);
2407 jme_reset_link(jme);
2410 set_bit(JME_FLAG_SSET, &jme->flags);
2411 jme->old_ecmd = *ecmd;
2420 struct jme_adapter *jme = netdev_priv(netdev);
2421 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2427 struct jme_adapter *jme = netdev_priv(netdev);
2428 return jme->msg_enable;
2434 struct jme_adapter *jme = netdev_priv(netdev);
2435 jme->msg_enable = value;
2441 struct jme_adapter *jme = netdev_priv(netdev);
2442 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2448 struct jme_adapter *jme = netdev_priv(netdev);
2450 spin_lock_bh(&jme->rxmcs_lock);
2452 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2454 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2455 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2456 spin_unlock_bh(&jme->rxmcs_lock);
2464 struct jme_adapter *jme = netdev_priv(netdev);
2467 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2471 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2481 struct jme_adapter *jme = netdev_priv(netdev);
2484 set_bit(JME_FLAG_TSO, &jme->flags);
2488 clear_bit(JME_FLAG_TSO, &jme->flags);
2498 struct jme_adapter *jme = netdev_priv(netdev);
2499 jme_restart_an(jme);
2504 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2509 val = jread32(jme, JME_SMBCSR);
2513 val = jread32(jme, JME_SMBCSR);
2516 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2520 jwrite32(jme, JME_SMBINTF,
2525 val = jread32(jme, JME_SMBINTF);
2529 val = jread32(jme, JME_SMBINTF);
2532 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2540 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2545 val = jread32(jme, JME_SMBCSR);
2549 val = jread32(jme, JME_SMBCSR);
2552 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2556 jwrite32(jme, JME_SMBINTF,
2562 val = jread32(jme, JME_SMBINTF);
2566 val = jread32(jme, JME_SMBINTF);
2569 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2579 struct jme_adapter *jme = netdev_priv(netdev);
2581 val = jread32(jme, JME_SMBCSR);
2589 struct jme_adapter *jme = netdev_priv(netdev);
2597 data[i] = jme_smb_read(jme, i + offset);
2606 struct jme_adapter *jme = netdev_priv(netdev);
2616 jme_smb_write(jme, i + offset, data[i]);
2668 jme_phy_init(struct jme_adapter *jme)
2672 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2673 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2677 jme_check_hw_ver(struct jme_adapter *jme)
2681 chipmode = jread32(jme, JME_CHIPMODE);
2683 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2684 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2705 struct jme_adapter *jme;
2742 netdev = alloc_etherdev(sizeof(*jme));
2766 jme = netdev_priv(netdev);
2767 jme->pdev = pdev;
2768 jme->dev = netdev;
2769 jme->jme_rx = netif_rx;
2770 jme->jme_vlan_rx = vlan_hwaccel_rx;
2771 jme->old_mtu = netdev->mtu = 1500;
2772 jme->phylink = 0;
2773 jme->tx_ring_size = 1 << 10;
2774 jme->tx_ring_mask = jme->tx_ring_size - 1;
2775 jme->tx_wake_threshold = 1 << 9;
2776 jme->rx_ring_size = 1 << 9;
2777 jme->rx_ring_mask = jme->rx_ring_size - 1;
2778 jme->msg_enable = JME_DEF_MSG_ENABLE;
2779 jme->regs = ioremap(pci_resource_start(pdev, 0),
2781 if (!(jme->regs)) {
2788 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2789 jwrite32(jme, JME_APMC, apmc);
2791 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2792 jwrite32(jme, JME_APMC, apmc);
2795 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2797 spin_lock_init(&jme->phy_lock);
2798 spin_lock_init(&jme->macaddr_lock);
2799 spin_lock_init(&jme->rxmcs_lock);
2801 atomic_set(&jme->link_changing, 1);
2802 atomic_set(&jme->rx_cleaning, 1);
2803 atomic_set(&jme->tx_cleaning, 1);
2804 atomic_set(&jme->rx_empty, 1);
2806 tasklet_init(&jme->pcc_task,
2808 (unsigned long) jme);
2809 tasklet_init(&jme->linkch_task,
2811 (unsigned long) jme);
2812 tasklet_init(&jme->txclean_task,
2814 (unsigned long) jme);
2815 tasklet_init(&jme->rxclean_task,
2817 (unsigned long) jme);
2818 tasklet_init(&jme->rxempty_task,
2820 (unsigned long) jme);
2821 tasklet_disable_nosync(&jme->linkch_task);
2822 tasklet_disable_nosync(&jme->txclean_task);
2823 tasklet_disable_nosync(&jme->rxclean_task);
2824 tasklet_disable_nosync(&jme->rxempty_task);
2825 jme->dpi.cur = PCC_P1;
2827 jme->reg_ghc = 0;
2828 jme->reg_rxcs = RXCS_DEFAULT;
2829 jme->reg_rxmcs = RXMCS_DEFAULT;
2830 jme->reg_txpfc = 0;
2831 jme->reg_pmcs = PMCS_MFEN;
2832 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2833 set_bit(JME_FLAG_TSO, &jme->flags);
2838 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2839 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2840 switch (jme->mrrs) {
2842 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2845 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2848 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2855 jme_check_hw_ver(jme);
2856 jme->mii_if.dev = netdev;
2857 if (jme->fpgaver) {
2858 jme->mii_if.phy_id = 0;
2863 jme->mii_if.phy_id = i;
2868 if (!jme->mii_if.phy_id) {
2874 jme->reg_ghc |= GHC_LINK_POLL;
2876 jme->mii_if.phy_id = 1;
2879 jme->mii_if.supports_gmii = true;
2881 jme->mii_if.supports_gmii = false;
2882 jme->mii_if.mdio_read = jme_mdio_read;
2883 jme->mii_if.mdio_write = jme_mdio_write;
2885 jme_clear_pm(jme);
2886 jme_set_phyfifoa(jme);
2887 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2888 if (!jme->fpgaver)
2889 jme_phy_init(jme);
2890 jme_phy_off(jme);
2895 jme_reset_mac_processor(jme);
2896 rc = jme_reload_eeprom(jme);
2919 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2920 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2922 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2924 (jme->fpgaver != 0) ? " (FPGA)" : "",
2925 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2926 jme->rev, netdev->dev_addr);
2931 iounmap(jme->regs);
2947 struct jme_adapter *jme = netdev_priv(netdev);
2950 iounmap(jme->regs);
2963 struct jme_adapter *jme = netdev_priv(netdev);
2965 atomic_dec(&jme->link_changing);
2969 jme_stop_irq(jme);
2971 tasklet_disable(&jme->txclean_task);
2972 tasklet_disable(&jme->rxclean_task);
2973 tasklet_disable(&jme->rxempty_task);
2976 if (test_bit(JME_FLAG_POLL, &jme->flags))
2977 jme_polling_mode(jme);
2979 jme_stop_pcc_timer(jme);
2980 jme_reset_ghc_speed(jme);
2981 jme_disable_rx_engine(jme);
2982 jme_disable_tx_engine(jme);
2983 jme_reset_mac_processor(jme);
2984 jme_free_rx_resources(jme);
2985 jme_free_tx_resources(jme);
2987 jme->phylink = 0;
2990 tasklet_enable(&jme->txclean_task);
2991 tasklet_hi_enable(&jme->rxclean_task);
2992 tasklet_hi_enable(&jme->rxempty_task);
2995 if (jme->reg_pmcs) {
2996 jme_set_100m_half(jme);
2998 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2999 jme_wait_link(jme);
3001 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3005 jme_phy_off(jme);
3016 struct jme_adapter *jme = netdev_priv(netdev);
3018 jme_clear_pm(jme);
3021 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3022 jme_phy_on(jme);
3023 jme_set_settings(netdev, &jme->old_ecmd);
3025 jme_reset_phy_processor(jme);
3028 jme_start_irq(jme);
3031 atomic_inc(&jme->link_changing);
3033 jme_reset_link(jme);