Lines Matching refs:bmwrite
168 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
203 bmwrite(dev, MIFCSR, 0);
207 bmwrite(dev, MIFCSR, 1);
210 bmwrite(dev, MIFCSR, 0);
212 bmwrite(dev, MIFCSR, 1);
224 bmwrite(dev, MIFCSR, b);
226 bmwrite(dev, MIFCSR, b|1);
236 bmwrite(dev, MIFCSR, 4);
241 bmwrite(dev, MIFCSR, 2);
243 bmwrite(dev, MIFCSR, 1);
246 bmwrite(dev, MIFCSR, 4);
254 bmwrite(dev, MIFCSR, 4);
274 bmwrite(dev, RXRST, RxResetValue);
275 bmwrite(dev, TXRST, TxResetBit);
287 bmwrite(dev, XCVRIF, regValue);
291 bmwrite(dev, RSEED, (unsigned short)0x1968);
295 bmwrite(dev, XIFC, regValue);
300 bmwrite(dev, NCCNT, 0);
301 bmwrite(dev, NTCNT, 0);
302 bmwrite(dev, EXCNT, 0);
303 bmwrite(dev, LTCNT, 0);
306 bmwrite(dev, FRCNT, 0);
307 bmwrite(dev, LECNT, 0);
308 bmwrite(dev, AECNT, 0);
309 bmwrite(dev, FECNT, 0);
310 bmwrite(dev, RXCV, 0);
313 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
315 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
316 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
319 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
320 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
322 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
327 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
328 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
329 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
330 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
333 bmwrite(dev, MADD0, *pWord16++);
334 bmwrite(dev, MADD1, *pWord16++);
335 bmwrite(dev, MADD2, *pWord16);
337 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
339 bmwrite(dev, INTDISABLE, EnableNormal);
355 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
359 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
423 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
425 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
426 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
482 bmwrite(dev, MADD0, *pWord16++);
483 bmwrite(dev, MADD1, *pWord16++);
484 bmwrite(dev, MADD2, *pWord16);
850 bmwrite(dev, RXCFG, rx_cfg);
867 bmwrite(dev, RXRST, RxResetValue);
868 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
869 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
870 bmwrite(dev, RXCFG, rx_cfg );
877 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
878 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
879 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
880 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
911 bmwrite(dev, RXCFG, rx_cfg);
943 bmwrite(dev, BHASH0, 0xffff);
944 bmwrite(dev, BHASH1, 0xffff);
945 bmwrite(dev, BHASH2, 0xffff);
946 bmwrite(dev, BHASH3, 0xffff);
950 bmwrite(dev, RXCFG, rx_cfg);
956 bmwrite(dev, RXCFG, rx_cfg);
970 bmwrite(dev, BHASH0, hash_table[0]);
971 bmwrite(dev, BHASH1, hash_table[1]);
972 bmwrite(dev, BHASH2, hash_table[2]);
973 bmwrite(dev, BHASH3, hash_table[3]);
1025 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1032 bmwrite(dev, SROMCSR, ChipSelect);
1046 bmwrite(dev, SROMCSR, data | ChipSelect );
1049 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1052 bmwrite(dev, SROMCSR, data | ChipSelect);
1060 bmwrite(dev, SROMCSR, 0);
1088 bmwrite(dev, SROMCSR, 0);
1139 bmwrite(dev, INTDISABLE, EnableNormal);
1229 bmwrite(dev, INTDISABLE, DisableAll);
1237 bmwrite(dev, INTDISABLE, DisableAll);
1342 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1345 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1347 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1437 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1439 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1476 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1478 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );