Lines Matching refs:zr36050_write
93 zr36050_write (struct zr36050 *ptr,
175 zr36050_write(ptr, ZR050_SOF_IDX, 0x00);
176 zr36050_write(ptr, ZR050_SOF_IDX + 1, 0x00);
185 zr36050_write(ptr, ZR050_SOF_IDX, 0xff);
186 zr36050_write(ptr, ZR050_SOF_IDX + 1, 0xc0);
225 zr36050_write(ptr, startreg++, data[i++]);
438 zr36050_write(ptr, ZR050_HARDWARE, ZR050_HW_MSTR);
441 zr36050_write(ptr, ZR050_MODE,
443 zr36050_write(ptr, ZR050_OPTIONS, 0);
446 zr36050_write(ptr, ZR050_INT_REQ_0, 0);
447 zr36050_write(ptr, ZR050_INT_REQ_1, 3); // low 2 bits always 1
450 /*zr36050_write(ptr, ZR050_MBCV, ptr->max_block_vol);*/
451 zr36050_write(ptr, ZR050_SF_HI, ptr->scalefact >> 8);
452 zr36050_write(ptr, ZR050_SF_LO, ptr->scalefact & 0xff);
454 zr36050_write(ptr, ZR050_AF_HI, 0xff);
455 zr36050_write(ptr, ZR050_AF_M, 0xff);
456 zr36050_write(ptr, ZR050_AF_LO, 0xff);
470 zr36050_write(ptr, ZR050_APP_IDX, 0xff);
471 zr36050_write(ptr, ZR050_APP_IDX + 1, 0xe0 + ptr->app.appn);
472 zr36050_write(ptr, ZR050_APP_IDX + 2, 0x00);
473 zr36050_write(ptr, ZR050_APP_IDX + 3, ptr->app.len + 2);
476 zr36050_write(ptr, ZR050_COM_IDX, 0xff);
477 zr36050_write(ptr, ZR050_COM_IDX + 1, 0xfe);
478 zr36050_write(ptr, ZR050_COM_IDX + 2, 0x00);
479 zr36050_write(ptr, ZR050_COM_IDX + 3, ptr->com.len + 2);
484 zr36050_write(ptr, ZR050_MARKERS_EN, ZR050_ME_DHTI);
486 zr36050_write(ptr, ZR050_GO, 1); // launch codec
507 zr36050_write(ptr, ZR050_TCV_NET_HI, tmp >> 8);
508 zr36050_write(ptr, ZR050_TCV_NET_MH, tmp & 0xff);
510 zr36050_write(ptr, ZR050_TCV_NET_ML, tmp >> 8);
511 zr36050_write(ptr, ZR050_TCV_NET_LO, tmp & 0xff);
519 zr36050_write(ptr, ZR050_TCV_DATA_HI, tmp >> 8);
520 zr36050_write(ptr, ZR050_TCV_DATA_MH, tmp & 0xff);
522 zr36050_write(ptr, ZR050_TCV_DATA_ML, tmp >> 8);
523 zr36050_write(ptr, ZR050_TCV_DATA_LO, tmp & 0xff);
526 zr36050_write(ptr, ZR050_MODE,
531 zr36050_write(ptr, ZR050_MARKERS_EN,
539 zr36050_write(ptr, ZR050_HARDWARE,
543 zr36050_write(ptr, ZR050_MODE, ZR050_MO_TLM);
546 zr36050_write(ptr, ZR050_INT_REQ_0, 0);
547 zr36050_write(ptr, ZR050_INT_REQ_1, 3); // low 2 bits always 1
554 zr36050_write(ptr, ZR050_MARKERS_EN, ZR050_ME_DHTI);
556 zr36050_write(ptr, ZR050_GO, 1); // launch codec
568 zr36050_write(ptr, ZR050_MODE, 0);
569 zr36050_write(ptr, ZR050_MARKERS_EN, 0);
638 zr36050_write(ptr, ZR050_MBCV, ptr->max_block_vol);