Lines Matching refs:state
298 static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
340 struct mxl5005s_state *state = fe->tuner_priv;
355 ByteTable[0] |= state->config->AgcMasterByte;
372 state->config->AgcMasterByte;
388 state->config->AgcMasterByte ;
405 struct mxl5005s_state *state = fe->tuner_priv;
406 state->TunerRegs_Num = TUNER_REGS_NUM ;
408 state->TunerRegs[0].Reg_Num = 9 ;
409 state->TunerRegs[0].Reg_Val = 0x40 ;
411 state->TunerRegs[1].Reg_Num = 11 ;
412 state->TunerRegs[1].Reg_Val = 0x19 ;
414 state->TunerRegs[2].Reg_Num = 12 ;
415 state->TunerRegs[2].Reg_Val = 0x60 ;
417 state->TunerRegs[3].Reg_Num = 13 ;
418 state->TunerRegs[3].Reg_Val = 0x00 ;
420 state->TunerRegs[4].Reg_Num = 14 ;
421 state->TunerRegs[4].Reg_Val = 0x00 ;
423 state->TunerRegs[5].Reg_Num = 15 ;
424 state->TunerRegs[5].Reg_Val = 0xC0 ;
426 state->TunerRegs[6].Reg_Num = 16 ;
427 state->TunerRegs[6].Reg_Val = 0x00 ;
429 state->TunerRegs[7].Reg_Num = 17 ;
430 state->TunerRegs[7].Reg_Val = 0x00 ;
432 state->TunerRegs[8].Reg_Num = 18 ;
433 state->TunerRegs[8].Reg_Val = 0x00 ;
435 state->TunerRegs[9].Reg_Num = 19 ;
436 state->TunerRegs[9].Reg_Val = 0x34 ;
438 state->TunerRegs[10].Reg_Num = 21 ;
439 state->TunerRegs[10].Reg_Val = 0x00 ;
441 state->TunerRegs[11].Reg_Num = 22 ;
442 state->TunerRegs[11].Reg_Val = 0x6B ;
444 state->TunerRegs[12].Reg_Num = 23 ;
445 state->TunerRegs[12].Reg_Val = 0x35 ;
447 state->TunerRegs[13].Reg_Num = 24 ;
448 state->TunerRegs[13].Reg_Val = 0x70 ;
450 state->TunerRegs[14].Reg_Num = 25 ;
451 state->TunerRegs[14].Reg_Val = 0x3E ;
453 state->TunerRegs[15].Reg_Num = 26 ;
454 state->TunerRegs[15].Reg_Val = 0x82 ;
456 state->TunerRegs[16].Reg_Num = 31 ;
457 state->TunerRegs[16].Reg_Val = 0x00 ;
459 state->TunerRegs[17].Reg_Num = 32 ;
460 state->TunerRegs[17].Reg_Val = 0x40 ;
462 state->TunerRegs[18].Reg_Num = 33 ;
463 state->TunerRegs[18].Reg_Val = 0x53 ;
465 state->TunerRegs[19].Reg_Num = 34 ;
466 state->TunerRegs[19].Reg_Val = 0x81 ;
468 state->TunerRegs[20].Reg_Num = 35 ;
469 state->TunerRegs[20].Reg_Val = 0xC9 ;
471 state->TunerRegs[21].Reg_Num = 36 ;
472 state->TunerRegs[21].Reg_Val = 0x01 ;
474 state->TunerRegs[22].Reg_Num = 37 ;
475 state->TunerRegs[22].Reg_Val = 0x00 ;
477 state->TunerRegs[23].Reg_Num = 41 ;
478 state->TunerRegs[23].Reg_Val = 0x00 ;
480 state->TunerRegs[24].Reg_Num = 42 ;
481 state->TunerRegs[24].Reg_Val = 0xF8 ;
483 state->TunerRegs[25].Reg_Num = 43 ;
484 state->TunerRegs[25].Reg_Val = 0x43 ;
486 state->TunerRegs[26].Reg_Num = 44 ;
487 state->TunerRegs[26].Reg_Val = 0x20 ;
489 state->TunerRegs[27].Reg_Num = 45 ;
490 state->TunerRegs[27].Reg_Val = 0x80 ;
492 state->TunerRegs[28].Reg_Num = 46 ;
493 state->TunerRegs[28].Reg_Val = 0x88 ;
495 state->TunerRegs[29].Reg_Num = 47 ;
496 state->TunerRegs[29].Reg_Val = 0x86 ;
498 state->TunerRegs[30].Reg_Num = 48 ;
499 state->TunerRegs[30].Reg_Val = 0x00 ;
501 state->TunerRegs[31].Reg_Num = 49 ;
502 state->TunerRegs[31].Reg_Val = 0x00 ;
504 state->TunerRegs[32].Reg_Num = 53 ;
505 state->TunerRegs[32].Reg_Val = 0x94 ;
507 state->TunerRegs[33].Reg_Num = 54 ;
508 state->TunerRegs[33].Reg_Val = 0xFA ;
510 state->TunerRegs[34].Reg_Num = 55 ;
511 state->TunerRegs[34].Reg_Val = 0x92 ;
513 state->TunerRegs[35].Reg_Num = 56 ;
514 state->TunerRegs[35].Reg_Val = 0x80 ;
516 state->TunerRegs[36].Reg_Num = 57 ;
517 state->TunerRegs[36].Reg_Val = 0x41 ;
519 state->TunerRegs[37].Reg_Num = 58 ;
520 state->TunerRegs[37].Reg_Val = 0xDB ;
522 state->TunerRegs[38].Reg_Num = 59 ;
523 state->TunerRegs[38].Reg_Val = 0x00 ;
525 state->TunerRegs[39].Reg_Num = 60 ;
526 state->TunerRegs[39].Reg_Val = 0x00 ;
528 state->TunerRegs[40].Reg_Num = 61 ;
529 state->TunerRegs[40].Reg_Val = 0x00 ;
531 state->TunerRegs[41].Reg_Num = 62 ;
532 state->TunerRegs[41].Reg_Val = 0x00 ;
534 state->TunerRegs[42].Reg_Num = 65 ;
535 state->TunerRegs[42].Reg_Val = 0xF8 ;
537 state->TunerRegs[43].Reg_Num = 66 ;
538 state->TunerRegs[43].Reg_Val = 0xE4 ;
540 state->TunerRegs[44].Reg_Num = 67 ;
541 state->TunerRegs[44].Reg_Val = 0x90 ;
543 state->TunerRegs[45].Reg_Num = 68 ;
544 state->TunerRegs[45].Reg_Val = 0xC0 ;
546 state->TunerRegs[46].Reg_Num = 69 ;
547 state->TunerRegs[46].Reg_Val = 0x01 ;
549 state->TunerRegs[47].Reg_Num = 70 ;
550 state->TunerRegs[47].Reg_Val = 0x50 ;
552 state->TunerRegs[48].Reg_Num = 71 ;
553 state->TunerRegs[48].Reg_Val = 0x06 ;
555 state->TunerRegs[49].Reg_Num = 72 ;
556 state->TunerRegs[49].Reg_Val = 0x00 ;
558 state->TunerRegs[50].Reg_Num = 73 ;
559 state->TunerRegs[50].Reg_Val = 0x20 ;
561 state->TunerRegs[51].Reg_Num = 76 ;
562 state->TunerRegs[51].Reg_Val = 0xBB ;
564 state->TunerRegs[52].Reg_Num = 77 ;
565 state->TunerRegs[52].Reg_Val = 0x13 ;
567 state->TunerRegs[53].Reg_Num = 81 ;
568 state->TunerRegs[53].Reg_Val = 0x04 ;
570 state->TunerRegs[54].Reg_Num = 82 ;
571 state->TunerRegs[54].Reg_Val = 0x75 ;
573 state->TunerRegs[55].Reg_Num = 83 ;
574 state->TunerRegs[55].Reg_Val = 0x00 ;
576 state->TunerRegs[56].Reg_Num = 84 ;
577 state->TunerRegs[56].Reg_Val = 0x00 ;
579 state->TunerRegs[57].Reg_Num = 85 ;
580 state->TunerRegs[57].Reg_Val = 0x00 ;
582 state->TunerRegs[58].Reg_Num = 91 ;
583 state->TunerRegs[58].Reg_Val = 0x70 ;
585 state->TunerRegs[59].Reg_Num = 92 ;
586 state->TunerRegs[59].Reg_Val = 0x00 ;
588 state->TunerRegs[60].Reg_Num = 93 ;
589 state->TunerRegs[60].Reg_Val = 0x00 ;
591 state->TunerRegs[61].Reg_Num = 94 ;
592 state->TunerRegs[61].Reg_Val = 0x00 ;
594 state->TunerRegs[62].Reg_Num = 95 ;
595 state->TunerRegs[62].Reg_Val = 0x0C ;
597 state->TunerRegs[63].Reg_Num = 96 ;
598 state->TunerRegs[63].Reg_Val = 0x00 ;
600 state->TunerRegs[64].Reg_Num = 97 ;
601 state->TunerRegs[64].Reg_Val = 0x00 ;
603 state->TunerRegs[65].Reg_Num = 98 ;
604 state->TunerRegs[65].Reg_Val = 0xE2 ;
606 state->TunerRegs[66].Reg_Num = 99 ;
607 state->TunerRegs[66].Reg_Val = 0x00 ;
609 state->TunerRegs[67].Reg_Num = 100 ;
610 state->TunerRegs[67].Reg_Val = 0x00 ;
612 state->TunerRegs[68].Reg_Num = 101 ;
613 state->TunerRegs[68].Reg_Val = 0x12 ;
615 state->TunerRegs[69].Reg_Num = 102 ;
616 state->TunerRegs[69].Reg_Val = 0x80 ;
618 state->TunerRegs[70].Reg_Num = 103 ;
619 state->TunerRegs[70].Reg_Val = 0x32 ;
621 state->TunerRegs[71].Reg_Num = 104 ;
622 state->TunerRegs[71].Reg_Val = 0xB4 ;
624 state->TunerRegs[72].Reg_Num = 105 ;
625 state->TunerRegs[72].Reg_Val = 0x60 ;
627 state->TunerRegs[73].Reg_Num = 106 ;
628 state->TunerRegs[73].Reg_Val = 0x83 ;
630 state->TunerRegs[74].Reg_Num = 107 ;
631 state->TunerRegs[74].Reg_Val = 0x84 ;
633 state->TunerRegs[75].Reg_Num = 108 ;
634 state->TunerRegs[75].Reg_Val = 0x9C ;
636 state->TunerRegs[76].Reg_Num = 109 ;
637 state->TunerRegs[76].Reg_Val = 0x02 ;
639 state->TunerRegs[77].Reg_Num = 110 ;
640 state->TunerRegs[77].Reg_Val = 0x81 ;
642 state->TunerRegs[78].Reg_Num = 111 ;
643 state->TunerRegs[78].Reg_Val = 0xC0 ;
645 state->TunerRegs[79].Reg_Num = 112 ;
646 state->TunerRegs[79].Reg_Val = 0x10 ;
648 state->TunerRegs[80].Reg_Num = 131 ;
649 state->TunerRegs[80].Reg_Val = 0x8A ;
651 state->TunerRegs[81].Reg_Num = 132 ;
652 state->TunerRegs[81].Reg_Val = 0x10 ;
654 state->TunerRegs[82].Reg_Num = 133 ;
655 state->TunerRegs[82].Reg_Val = 0x24 ;
657 state->TunerRegs[83].Reg_Num = 134 ;
658 state->TunerRegs[83].Reg_Val = 0x00 ;
660 state->TunerRegs[84].Reg_Num = 135 ;
661 state->TunerRegs[84].Reg_Val = 0x00 ;
663 state->TunerRegs[85].Reg_Num = 136 ;
664 state->TunerRegs[85].Reg_Val = 0x7E ;
666 state->TunerRegs[86].Reg_Num = 137 ;
667 state->TunerRegs[86].Reg_Val = 0x40 ;
669 state->TunerRegs[87].Reg_Num = 138 ;
670 state->TunerRegs[87].Reg_Val = 0x38 ;
672 state->TunerRegs[88].Reg_Num = 146 ;
673 state->TunerRegs[88].Reg_Val = 0xF6 ;
675 state->TunerRegs[89].Reg_Num = 147 ;
676 state->TunerRegs[89].Reg_Val = 0x1A ;
678 state->TunerRegs[90].Reg_Num = 148 ;
679 state->TunerRegs[90].Reg_Val = 0x62 ;
681 state->TunerRegs[91].Reg_Num = 149 ;
682 state->TunerRegs[91].Reg_Val = 0x33 ;
684 state->TunerRegs[92].Reg_Num = 150 ;
685 state->TunerRegs[92].Reg_Val = 0x80 ;
687 state->TunerRegs[93].Reg_Num = 156 ;
688 state->TunerRegs[93].Reg_Val = 0x56 ;
690 state->TunerRegs[94].Reg_Num = 157 ;
691 state->TunerRegs[94].Reg_Val = 0x17 ;
693 state->TunerRegs[95].Reg_Num = 158 ;
694 state->TunerRegs[95].Reg_Val = 0xA9 ;
696 state->TunerRegs[96].Reg_Num = 159 ;
697 state->TunerRegs[96].Reg_Val = 0x00 ;
699 state->TunerRegs[97].Reg_Num = 160 ;
700 state->TunerRegs[97].Reg_Val = 0x00 ;
702 state->TunerRegs[98].Reg_Num = 161 ;
703 state->TunerRegs[98].Reg_Val = 0x00 ;
705 state->TunerRegs[99].Reg_Num = 162 ;
706 state->TunerRegs[99].Reg_Val = 0x40 ;
708 state->TunerRegs[100].Reg_Num = 166 ;
709 state->TunerRegs[100].Reg_Val = 0xAE ;
711 state->TunerRegs[101].Reg_Num = 167 ;
712 state->TunerRegs[101].Reg_Val = 0x1B ;
714 state->TunerRegs[102].Reg_Num = 168 ;
715 state->TunerRegs[102].Reg_Val = 0xF2 ;
717 state->TunerRegs[103].Reg_Num = 195 ;
718 state->TunerRegs[103].Reg_Val = 0x00 ;
725 struct mxl5005s_state *state = fe->tuner_priv;
726 state->Init_Ctrl_Num = INITCTRL_NUM;
728 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
729 state->Init_Ctrl[0].size = 1 ;
730 state->Init_Ctrl[0].addr[0] = 73;
731 state->Init_Ctrl[0].bit[0] = 7;
732 state->Init_Ctrl[0].val[0] = 0;
734 state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
735 state->Init_Ctrl[1].size = 1 ;
736 state->Init_Ctrl[1].addr[0] = 53;
737 state->Init_Ctrl[1].bit[0] = 2;
738 state->Init_Ctrl[1].val[0] = 1;
740 state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
741 state->Init_Ctrl[2].size = 2 ;
742 state->Init_Ctrl[2].addr[0] = 53;
743 state->Init_Ctrl[2].bit[0] = 1;
744 state->Init_Ctrl[2].val[0] = 0;
745 state->Init_Ctrl[2].addr[1] = 57;
746 state->Init_Ctrl[2].bit[1] = 0;
747 state->Init_Ctrl[2].val[1] = 1;
749 state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
750 state->Init_Ctrl[3].size = 1 ;
751 state->Init_Ctrl[3].addr[0] = 53;
752 state->Init_Ctrl[3].bit[0] = 0;
753 state->Init_Ctrl[3].val[0] = 0;
755 state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
756 state->Init_Ctrl[4].size = 3 ;
757 state->Init_Ctrl[4].addr[0] = 53;
758 state->Init_Ctrl[4].bit[0] = 5;
759 state->Init_Ctrl[4].val[0] = 0;
760 state->Init_Ctrl[4].addr[1] = 53;
761 state->Init_Ctrl[4].bit[1] = 6;
762 state->Init_Ctrl[4].val[1] = 0;
763 state->Init_Ctrl[4].addr[2] = 53;
764 state->Init_Ctrl[4].bit[2] = 7;
765 state->Init_Ctrl[4].val[2] = 1;
767 state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
768 state->Init_Ctrl[5].size = 1 ;
769 state->Init_Ctrl[5].addr[0] = 59;
770 state->Init_Ctrl[5].bit[0] = 0;
771 state->Init_Ctrl[5].val[0] = 0;
773 state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
774 state->Init_Ctrl[6].size = 2 ;
775 state->Init_Ctrl[6].addr[0] = 53;
776 state->Init_Ctrl[6].bit[0] = 3;
777 state->Init_Ctrl[6].val[0] = 0;
778 state->Init_Ctrl[6].addr[1] = 53;
779 state->Init_Ctrl[6].bit[1] = 4;
780 state->Init_Ctrl[6].val[1] = 1;
782 state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
783 state->Init_Ctrl[7].size = 4 ;
784 state->Init_Ctrl[7].addr[0] = 22;
785 state->Init_Ctrl[7].bit[0] = 4;
786 state->Init_Ctrl[7].val[0] = 0;
787 state->Init_Ctrl[7].addr[1] = 22;
788 state->Init_Ctrl[7].bit[1] = 5;
789 state->Init_Ctrl[7].val[1] = 1;
790 state->Init_Ctrl[7].addr[2] = 22;
791 state->Init_Ctrl[7].bit[2] = 6;
792 state->Init_Ctrl[7].val[2] = 1;
793 state->Init_Ctrl[7].addr[3] = 22;
794 state->Init_Ctrl[7].bit[3] = 7;
795 state->Init_Ctrl[7].val[3] = 0;
797 state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
798 state->Init_Ctrl[8].size = 1 ;
799 state->Init_Ctrl[8].addr[0] = 22;
800 state->Init_Ctrl[8].bit[0] = 2;
801 state->Init_Ctrl[8].val[0] = 0;
803 state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
804 state->Init_Ctrl[9].size = 4 ;
805 state->Init_Ctrl[9].addr[0] = 76;
806 state->Init_Ctrl[9].bit[0] = 0;
807 state->Init_Ctrl[9].val[0] = 1;
808 state->Init_Ctrl[9].addr[1] = 76;
809 state->Init_Ctrl[9].bit[1] = 1;
810 state->Init_Ctrl[9].val[1] = 1;
811 state->Init_Ctrl[9].addr[2] = 76;
812 state->Init_Ctrl[9].bit[2] = 2;
813 state->Init_Ctrl[9].val[2] = 0;
814 state->Init_Ctrl[9].addr[3] = 76;
815 state->Init_Ctrl[9].bit[3] = 3;
816 state->Init_Ctrl[9].val[3] = 1;
818 state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
819 state->Init_Ctrl[10].size = 4 ;
820 state->Init_Ctrl[10].addr[0] = 76;
821 state->Init_Ctrl[10].bit[0] = 4;
822 state->Init_Ctrl[10].val[0] = 1;
823 state->Init_Ctrl[10].addr[1] = 76;
824 state->Init_Ctrl[10].bit[1] = 5;
825 state->Init_Ctrl[10].val[1] = 1;
826 state->Init_Ctrl[10].addr[2] = 76;
827 state->Init_Ctrl[10].bit[2] = 6;
828 state->Init_Ctrl[10].val[2] = 0;
829 state->Init_Ctrl[10].addr[3] = 76;
830 state->Init_Ctrl[10].bit[3] = 7;
831 state->Init_Ctrl[10].val[3] = 1;
833 state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
834 state->Init_Ctrl[11].size = 5 ;
835 state->Init_Ctrl[11].addr[0] = 43;
836 state->Init_Ctrl[11].bit[0] = 3;
837 state->Init_Ctrl[11].val[0] = 0;
838 state->Init_Ctrl[11].addr[1] = 43;
839 state->Init_Ctrl[11].bit[1] = 4;
840 state->Init_Ctrl[11].val[1] = 0;
841 state->Init_Ctrl[11].addr[2] = 43;
842 state->Init_Ctrl[11].bit[2] = 5;
843 state->Init_Ctrl[11].val[2] = 0;
844 state->Init_Ctrl[11].addr[3] = 43;
845 state->Init_Ctrl[11].bit[3] = 6;
846 state->Init_Ctrl[11].val[3] = 1;
847 state->Init_Ctrl[11].addr[4] = 43;
848 state->Init_Ctrl[11].bit[4] = 7;
849 state->Init_Ctrl[11].val[4] = 0;
851 state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
852 state->Init_Ctrl[12].size = 6 ;
853 state->Init_Ctrl[12].addr[0] = 44;
854 state->Init_Ctrl[12].bit[0] = 2;
855 state->Init_Ctrl[12].val[0] = 0;
856 state->Init_Ctrl[12].addr[1] = 44;
857 state->Init_Ctrl[12].bit[1] = 3;
858 state->Init_Ctrl[12].val[1] = 0;
859 state->Init_Ctrl[12].addr[2] = 44;
860 state->Init_Ctrl[12].bit[2] = 4;
861 state->Init_Ctrl[12].val[2] = 0;
862 state->Init_Ctrl[12].addr[3] = 44;
863 state->Init_Ctrl[12].bit[3] = 5;
864 state->Init_Ctrl[12].val[3] = 1;
865 state->Init_Ctrl[12].addr[4] = 44;
866 state->Init_Ctrl[12].bit[4] = 6;
867 state->Init_Ctrl[12].val[4] = 0;
868 state->Init_Ctrl[12].addr[5] = 44;
869 state->Init_Ctrl[12].bit[5] = 7;
870 state->Init_Ctrl[12].val[5] = 0;
872 state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
873 state->Init_Ctrl[13].size = 7 ;
874 state->Init_Ctrl[13].addr[0] = 11;
875 state->Init_Ctrl[13].bit[0] = 0;
876 state->Init_Ctrl[13].val[0] = 1;
877 state->Init_Ctrl[13].addr[1] = 11;
878 state->Init_Ctrl[13].bit[1] = 1;
879 state->Init_Ctrl[13].val[1] = 0;
880 state->Init_Ctrl[13].addr[2] = 11;
881 state->Init_Ctrl[13].bit[2] = 2;
882 state->Init_Ctrl[13].val[2] = 0;
883 state->Init_Ctrl[13].addr[3] = 11;
884 state->Init_Ctrl[13].bit[3] = 3;
885 state->Init_Ctrl[13].val[3] = 1;
886 state->Init_Ctrl[13].addr[4] = 11;
887 state->Init_Ctrl[13].bit[4] = 4;
888 state->Init_Ctrl[13].val[4] = 1;
889 state->Init_Ctrl[13].addr[5] = 11;
890 state->Init_Ctrl[13].bit[5] = 5;
891 state->Init_Ctrl[13].val[5] = 0;
892 state->Init_Ctrl[13].addr[6] = 11;
893 state->Init_Ctrl[13].bit[6] = 6;
894 state->Init_Ctrl[13].val[6] = 0;
896 state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
897 state->Init_Ctrl[14].size = 16 ;
898 state->Init_Ctrl[14].addr[0] = 13;
899 state->Init_Ctrl[14].bit[0] = 0;
900 state->Init_Ctrl[14].val[0] = 0;
901 state->Init_Ctrl[14].addr[1] = 13;
902 state->Init_Ctrl[14].bit[1] = 1;
903 state->Init_Ctrl[14].val[1] = 0;
904 state->Init_Ctrl[14].addr[2] = 13;
905 state->Init_Ctrl[14].bit[2] = 2;
906 state->Init_Ctrl[14].val[2] = 0;
907 state->Init_Ctrl[14].addr[3] = 13;
908 state->Init_Ctrl[14].bit[3] = 3;
909 state->Init_Ctrl[14].val[3] = 0;
910 state->Init_Ctrl[14].addr[4] = 13;
911 state->Init_Ctrl[14].bit[4] = 4;
912 state->Init_Ctrl[14].val[4] = 0;
913 state->Init_Ctrl[14].addr[5] = 13;
914 state->Init_Ctrl[14].bit[5] = 5;
915 state->Init_Ctrl[14].val[5] = 0;
916 state->Init_Ctrl[14].addr[6] = 13;
917 state->Init_Ctrl[14].bit[6] = 6;
918 state->Init_Ctrl[14].val[6] = 0;
919 state->Init_Ctrl[14].addr[7] = 13;
920 state->Init_Ctrl[14].bit[7] = 7;
921 state->Init_Ctrl[14].val[7] = 0;
922 state->Init_Ctrl[14].addr[8] = 12;
923 state->Init_Ctrl[14].bit[8] = 0;
924 state->Init_Ctrl[14].val[8] = 0;
925 state->Init_Ctrl[14].addr[9] = 12;
926 state->Init_Ctrl[14].bit[9] = 1;
927 state->Init_Ctrl[14].val[9] = 0;
928 state->Init_Ctrl[14].addr[10] = 12;
929 state->Init_Ctrl[14].bit[10] = 2;
930 state->Init_Ctrl[14].val[10] = 0;
931 state->Init_Ctrl[14].addr[11] = 12;
932 state->Init_Ctrl[14].bit[11] = 3;
933 state->Init_Ctrl[14].val[11] = 0;
934 state->Init_Ctrl[14].addr[12] = 12;
935 state->Init_Ctrl[14].bit[12] = 4;
936 state->Init_Ctrl[14].val[12] = 0;
937 state->Init_Ctrl[14].addr[13] = 12;
938 state->Init_Ctrl[14].bit[13] = 5;
939 state->Init_Ctrl[14].val[13] = 1;
940 state->Init_Ctrl[14].addr[14] = 12;
941 state->Init_Ctrl[14].bit[14] = 6;
942 state->Init_Ctrl[14].val[14] = 1;
943 state->Init_Ctrl[14].addr[15] = 12;
944 state->Init_Ctrl[14].bit[15] = 7;
945 state->Init_Ctrl[14].val[15] = 0;
947 state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
948 state->Init_Ctrl[15].size = 3 ;
949 state->Init_Ctrl[15].addr[0] = 147;
950 state->Init_Ctrl[15].bit[0] = 2;
951 state->Init_Ctrl[15].val[0] = 0;
952 state->Init_Ctrl[15].addr[1] = 147;
953 state->Init_Ctrl[15].bit[1] = 3;
954 state->Init_Ctrl[15].val[1] = 1;
955 state->Init_Ctrl[15].addr[2] = 147;
956 state->Init_Ctrl[15].bit[2] = 4;
957 state->Init_Ctrl[15].val[2] = 1;
959 state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
960 state->Init_Ctrl[16].size = 2 ;
961 state->Init_Ctrl[16].addr[0] = 147;
962 state->Init_Ctrl[16].bit[0] = 0;
963 state->Init_Ctrl[16].val[0] = 0;
964 state->Init_Ctrl[16].addr[1] = 147;
965 state->Init_Ctrl[16].bit[1] = 1;
966 state->Init_Ctrl[16].val[1] = 1;
968 state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
969 state->Init_Ctrl[17].size = 1 ;
970 state->Init_Ctrl[17].addr[0] = 147;
971 state->Init_Ctrl[17].bit[0] = 7;
972 state->Init_Ctrl[17].val[0] = 0;
974 state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
975 state->Init_Ctrl[18].size = 1 ;
976 state->Init_Ctrl[18].addr[0] = 147;
977 state->Init_Ctrl[18].bit[0] = 6;
978 state->Init_Ctrl[18].val[0] = 0;
980 state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
981 state->Init_Ctrl[19].size = 1 ;
982 state->Init_Ctrl[19].addr[0] = 156;
983 state->Init_Ctrl[19].bit[0] = 0;
984 state->Init_Ctrl[19].val[0] = 0;
986 state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
987 state->Init_Ctrl[20].size = 1 ;
988 state->Init_Ctrl[20].addr[0] = 147;
989 state->Init_Ctrl[20].bit[0] = 5;
990 state->Init_Ctrl[20].val[0] = 0;
992 state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
993 state->Init_Ctrl[21].size = 1 ;
994 state->Init_Ctrl[21].addr[0] = 137;
995 state->Init_Ctrl[21].bit[0] = 4;
996 state->Init_Ctrl[21].val[0] = 0;
998 state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
999 state->Init_Ctrl[22].size = 1 ;
1000 state->Init_Ctrl[22].addr[0] = 137;
1001 state->Init_Ctrl[22].bit[0] = 7;
1002 state->Init_Ctrl[22].val[0] = 0;
1004 state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1005 state->Init_Ctrl[23].size = 1 ;
1006 state->Init_Ctrl[23].addr[0] = 91;
1007 state->Init_Ctrl[23].bit[0] = 5;
1008 state->Init_Ctrl[23].val[0] = 1;
1010 state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1011 state->Init_Ctrl[24].size = 1 ;
1012 state->Init_Ctrl[24].addr[0] = 43;
1013 state->Init_Ctrl[24].bit[0] = 0;
1014 state->Init_Ctrl[24].val[0] = 1;
1016 state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1017 state->Init_Ctrl[25].size = 2 ;
1018 state->Init_Ctrl[25].addr[0] = 22;
1019 state->Init_Ctrl[25].bit[0] = 0;
1020 state->Init_Ctrl[25].val[0] = 1;
1021 state->Init_Ctrl[25].addr[1] = 22;
1022 state->Init_Ctrl[25].bit[1] = 1;
1023 state->Init_Ctrl[25].val[1] = 1;
1025 state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1026 state->Init_Ctrl[26].size = 1 ;
1027 state->Init_Ctrl[26].addr[0] = 134;
1028 state->Init_Ctrl[26].bit[0] = 2;
1029 state->Init_Ctrl[26].val[0] = 0;
1031 state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1032 state->Init_Ctrl[27].size = 1 ;
1033 state->Init_Ctrl[27].addr[0] = 137;
1034 state->Init_Ctrl[27].bit[0] = 3;
1035 state->Init_Ctrl[27].val[0] = 0;
1037 state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1038 state->Init_Ctrl[28].size = 1 ;
1039 state->Init_Ctrl[28].addr[0] = 77;
1040 state->Init_Ctrl[28].bit[0] = 7;
1041 state->Init_Ctrl[28].val[0] = 0;
1043 state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1044 state->Init_Ctrl[29].size = 1 ;
1045 state->Init_Ctrl[29].addr[0] = 166;
1046 state->Init_Ctrl[29].bit[0] = 7;
1047 state->Init_Ctrl[29].val[0] = 1;
1049 state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1050 state->Init_Ctrl[30].size = 3 ;
1051 state->Init_Ctrl[30].addr[0] = 166;
1052 state->Init_Ctrl[30].bit[0] = 0;
1053 state->Init_Ctrl[30].val[0] = 0;
1054 state->Init_Ctrl[30].addr[1] = 166;
1055 state->Init_Ctrl[30].bit[1] = 1;
1056 state->Init_Ctrl[30].val[1] = 1;
1057 state->Init_Ctrl[30].addr[2] = 166;
1058 state->Init_Ctrl[30].bit[2] = 2;
1059 state->Init_Ctrl[30].val[2] = 1;
1061 state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1062 state->Init_Ctrl[31].size = 3 ;
1063 state->Init_Ctrl[31].addr[0] = 166;
1064 state->Init_Ctrl[31].bit[0] = 3;
1065 state->Init_Ctrl[31].val[0] = 1;
1066 state->Init_Ctrl[31].addr[1] = 166;
1067 state->Init_Ctrl[31].bit[1] = 4;
1068 state->Init_Ctrl[31].val[1] = 0;
1069 state->Init_Ctrl[31].addr[2] = 166;
1070 state->Init_Ctrl[31].bit[2] = 5;
1071 state->Init_Ctrl[31].val[2] = 1;
1073 state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1074 state->Init_Ctrl[32].size = 3 ;
1075 state->Init_Ctrl[32].addr[0] = 167;
1076 state->Init_Ctrl[32].bit[0] = 0;
1077 state->Init_Ctrl[32].val[0] = 1;
1078 state->Init_Ctrl[32].addr[1] = 167;
1079 state->Init_Ctrl[32].bit[1] = 1;
1080 state->Init_Ctrl[32].val[1] = 1;
1081 state->Init_Ctrl[32].addr[2] = 167;
1082 state->Init_Ctrl[32].bit[2] = 2;
1083 state->Init_Ctrl[32].val[2] = 0;
1085 state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1086 state->Init_Ctrl[33].size = 4 ;
1087 state->Init_Ctrl[33].addr[0] = 168;
1088 state->Init_Ctrl[33].bit[0] = 0;
1089 state->Init_Ctrl[33].val[0] = 0;
1090 state->Init_Ctrl[33].addr[1] = 168;
1091 state->Init_Ctrl[33].bit[1] = 1;
1092 state->Init_Ctrl[33].val[1] = 1;
1093 state->Init_Ctrl[33].addr[2] = 168;
1094 state->Init_Ctrl[33].bit[2] = 2;
1095 state->Init_Ctrl[33].val[2] = 0;
1096 state->Init_Ctrl[33].addr[3] = 168;
1097 state->Init_Ctrl[33].bit[3] = 3;
1098 state->Init_Ctrl[33].val[3] = 0;
1100 state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1101 state->Init_Ctrl[34].size = 4 ;
1102 state->Init_Ctrl[34].addr[0] = 168;
1103 state->Init_Ctrl[34].bit[0] = 4;
1104 state->Init_Ctrl[34].val[0] = 1;
1105 state->Init_Ctrl[34].addr[1] = 168;
1106 state->Init_Ctrl[34].bit[1] = 5;
1107 state->Init_Ctrl[34].val[1] = 1;
1108 state->Init_Ctrl[34].addr[2] = 168;
1109 state->Init_Ctrl[34].bit[2] = 6;
1110 state->Init_Ctrl[34].val[2] = 1;
1111 state->Init_Ctrl[34].addr[3] = 168;
1112 state->Init_Ctrl[34].bit[3] = 7;
1113 state->Init_Ctrl[34].val[3] = 1;
1115 state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1116 state->Init_Ctrl[35].size = 1 ;
1117 state->Init_Ctrl[35].addr[0] = 135;
1118 state->Init_Ctrl[35].bit[0] = 0;
1119 state->Init_Ctrl[35].val[0] = 0;
1121 state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1122 state->Init_Ctrl[36].size = 1 ;
1123 state->Init_Ctrl[36].addr[0] = 56;
1124 state->Init_Ctrl[36].bit[0] = 3;
1125 state->Init_Ctrl[36].val[0] = 0;
1127 state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1128 state->Init_Ctrl[37].size = 7 ;
1129 state->Init_Ctrl[37].addr[0] = 59;
1130 state->Init_Ctrl[37].bit[0] = 1;
1131 state->Init_Ctrl[37].val[0] = 0;
1132 state->Init_Ctrl[37].addr[1] = 59;
1133 state->Init_Ctrl[37].bit[1] = 2;
1134 state->Init_Ctrl[37].val[1] = 0;
1135 state->Init_Ctrl[37].addr[2] = 59;
1136 state->Init_Ctrl[37].bit[2] = 3;
1137 state->Init_Ctrl[37].val[2] = 0;
1138 state->Init_Ctrl[37].addr[3] = 59;
1139 state->Init_Ctrl[37].bit[3] = 4;
1140 state->Init_Ctrl[37].val[3] = 0;
1141 state->Init_Ctrl[37].addr[4] = 59;
1142 state->Init_Ctrl[37].bit[4] = 5;
1143 state->Init_Ctrl[37].val[4] = 0;
1144 state->Init_Ctrl[37].addr[5] = 59;
1145 state->Init_Ctrl[37].bit[5] = 6;
1146 state->Init_Ctrl[37].val[5] = 0;
1147 state->Init_Ctrl[37].addr[6] = 59;
1148 state->Init_Ctrl[37].bit[6] = 7;
1149 state->Init_Ctrl[37].val[6] = 0;
1151 state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1152 state->Init_Ctrl[38].size = 6 ;
1153 state->Init_Ctrl[38].addr[0] = 32;
1154 state->Init_Ctrl[38].bit[0] = 2;
1155 state->Init_Ctrl[38].val[0] = 0;
1156 state->Init_Ctrl[38].addr[1] = 32;
1157 state->Init_Ctrl[38].bit[1] = 3;
1158 state->Init_Ctrl[38].val[1] = 0;
1159 state->Init_Ctrl[38].addr[2] = 32;
1160 state->Init_Ctrl[38].bit[2] = 4;
1161 state->Init_Ctrl[38].val[2] = 0;
1162 state->Init_Ctrl[38].addr[3] = 32;
1163 state->Init_Ctrl[38].bit[3] = 5;
1164 state->Init_Ctrl[38].val[3] = 0;
1165 state->Init_Ctrl[38].addr[4] = 32;
1166 state->Init_Ctrl[38].bit[4] = 6;
1167 state->Init_Ctrl[38].val[4] = 1;
1168 state->Init_Ctrl[38].addr[5] = 32;
1169 state->Init_Ctrl[38].bit[5] = 7;
1170 state->Init_Ctrl[38].val[5] = 0;
1172 state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1173 state->Init_Ctrl[39].size = 1 ;
1174 state->Init_Ctrl[39].addr[0] = 25;
1175 state->Init_Ctrl[39].bit[0] = 3;
1176 state->Init_Ctrl[39].val[0] = 1;
1179 state->CH_Ctrl_Num = CHCTRL_NUM ;
1181 state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1182 state->CH_Ctrl[0].size = 2 ;
1183 state->CH_Ctrl[0].addr[0] = 68;
1184 state->CH_Ctrl[0].bit[0] = 6;
1185 state->CH_Ctrl[0].val[0] = 1;
1186 state->CH_Ctrl[0].addr[1] = 68;
1187 state->CH_Ctrl[0].bit[1] = 7;
1188 state->CH_Ctrl[0].val[1] = 1;
1190 state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1191 state->CH_Ctrl[1].size = 2 ;
1192 state->CH_Ctrl[1].addr[0] = 70;
1193 state->CH_Ctrl[1].bit[0] = 6;
1194 state->CH_Ctrl[1].val[0] = 1;
1195 state->CH_Ctrl[1].addr[1] = 70;
1196 state->CH_Ctrl[1].bit[1] = 7;
1197 state->CH_Ctrl[1].val[1] = 0;
1199 state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1200 state->CH_Ctrl[2].size = 9 ;
1201 state->CH_Ctrl[2].addr[0] = 69;
1202 state->CH_Ctrl[2].bit[0] = 5;
1203 state->CH_Ctrl[2].val[0] = 0;
1204 state->CH_Ctrl[2].addr[1] = 69;
1205 state->CH_Ctrl[2].bit[1] = 6;
1206 state->CH_Ctrl[2].val[1] = 0;
1207 state->CH_Ctrl[2].addr[2] = 69;
1208 state->CH_Ctrl[2].bit[2] = 7;
1209 state->CH_Ctrl[2].val[2] = 0;
1210 state->CH_Ctrl[2].addr[3] = 68;
1211 state->CH_Ctrl[2].bit[3] = 0;
1212 state->CH_Ctrl[2].val[3] = 0;
1213 state->CH_Ctrl[2].addr[4] = 68;
1214 state->CH_Ctrl[2].bit[4] = 1;
1215 state->CH_Ctrl[2].val[4] = 0;
1216 state->CH_Ctrl[2].addr[5] = 68;
1217 state->CH_Ctrl[2].bit[5] = 2;
1218 state->CH_Ctrl[2].val[5] = 0;
1219 state->CH_Ctrl[2].addr[6] = 68;
1220 state->CH_Ctrl[2].bit[6] = 3;
1221 state->CH_Ctrl[2].val[6] = 0;
1222 state->CH_Ctrl[2].addr[7] = 68;
1223 state->CH_Ctrl[2].bit[7] = 4;
1224 state->CH_Ctrl[2].val[7] = 0;
1225 state->CH_Ctrl[2].addr[8] = 68;
1226 state->CH_Ctrl[2].bit[8] = 5;
1227 state->CH_Ctrl[2].val[8] = 0;
1229 state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1230 state->CH_Ctrl[3].size = 1 ;
1231 state->CH_Ctrl[3].addr[0] = 70;
1232 state->CH_Ctrl[3].bit[0] = 5;
1233 state->CH_Ctrl[3].val[0] = 0;
1235 state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1236 state->CH_Ctrl[4].size = 3 ;
1237 state->CH_Ctrl[4].addr[0] = 73;
1238 state->CH_Ctrl[4].bit[0] = 4;
1239 state->CH_Ctrl[4].val[0] = 0;
1240 state->CH_Ctrl[4].addr[1] = 73;
1241 state->CH_Ctrl[4].bit[1] = 5;
1242 state->CH_Ctrl[4].val[1] = 1;
1243 state->CH_Ctrl[4].addr[2] = 73;
1244 state->CH_Ctrl[4].bit[2] = 6;
1245 state->CH_Ctrl[4].val[2] = 0;
1247 state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1248 state->CH_Ctrl[5].size = 4 ;
1249 state->CH_Ctrl[5].addr[0] = 70;
1250 state->CH_Ctrl[5].bit[0] = 0;
1251 state->CH_Ctrl[5].val[0] = 0;
1252 state->CH_Ctrl[5].addr[1] = 70;
1253 state->CH_Ctrl[5].bit[1] = 1;
1254 state->CH_Ctrl[5].val[1] = 0;
1255 state->CH_Ctrl[5].addr[2] = 70;
1256 state->CH_Ctrl[5].bit[2] = 2;
1257 state->CH_Ctrl[5].val[2] = 0;
1258 state->CH_Ctrl[5].addr[3] = 70;
1259 state->CH_Ctrl[5].bit[3] = 3;
1260 state->CH_Ctrl[5].val[3] = 0;
1262 state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1263 state->CH_Ctrl[6].size = 1 ;
1264 state->CH_Ctrl[6].addr[0] = 70;
1265 state->CH_Ctrl[6].bit[0] = 4;
1266 state->CH_Ctrl[6].val[0] = 1;
1268 state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1269 state->CH_Ctrl[7].size = 1 ;
1270 state->CH_Ctrl[7].addr[0] = 111;
1271 state->CH_Ctrl[7].bit[0] = 4;
1272 state->CH_Ctrl[7].val[0] = 0;
1274 state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1275 state->CH_Ctrl[8].size = 1 ;
1276 state->CH_Ctrl[8].addr[0] = 111;
1277 state->CH_Ctrl[8].bit[0] = 7;
1278 state->CH_Ctrl[8].val[0] = 1;
1280 state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1281 state->CH_Ctrl[9].size = 1 ;
1282 state->CH_Ctrl[9].addr[0] = 111;
1283 state->CH_Ctrl[9].bit[0] = 6;
1284 state->CH_Ctrl[9].val[0] = 1;
1286 state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1287 state->CH_Ctrl[10].size = 1 ;
1288 state->CH_Ctrl[10].addr[0] = 111;
1289 state->CH_Ctrl[10].bit[0] = 5;
1290 state->CH_Ctrl[10].val[0] = 0;
1292 state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1293 state->CH_Ctrl[11].size = 2 ;
1294 state->CH_Ctrl[11].addr[0] = 110;
1295 state->CH_Ctrl[11].bit[0] = 0;
1296 state->CH_Ctrl[11].val[0] = 1;
1297 state->CH_Ctrl[11].addr[1] = 110;
1298 state->CH_Ctrl[11].bit[1] = 1;
1299 state->CH_Ctrl[11].val[1] = 0;
1301 state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1302 state->CH_Ctrl[12].size = 3 ;
1303 state->CH_Ctrl[12].addr[0] = 69;
1304 state->CH_Ctrl[12].bit[0] = 2;
1305 state->CH_Ctrl[12].val[0] = 0;
1306 state->CH_Ctrl[12].addr[1] = 69;
1307 state->CH_Ctrl[12].bit[1] = 3;
1308 state->CH_Ctrl[12].val[1] = 0;
1309 state->CH_Ctrl[12].addr[2] = 69;
1310 state->CH_Ctrl[12].bit[2] = 4;
1311 state->CH_Ctrl[12].val[2] = 0;
1313 state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1314 state->CH_Ctrl[13].size = 6 ;
1315 state->CH_Ctrl[13].addr[0] = 110;
1316 state->CH_Ctrl[13].bit[0] = 2;
1317 state->CH_Ctrl[13].val[0] = 0;
1318 state->CH_Ctrl[13].addr[1] = 110;
1319 state->CH_Ctrl[13].bit[1] = 3;
1320 state->CH_Ctrl[13].val[1] = 0;
1321 state->CH_Ctrl[13].addr[2] = 110;
1322 state->CH_Ctrl[13].bit[2] = 4;
1323 state->CH_Ctrl[13].val[2] = 0;
1324 state->CH_Ctrl[13].addr[3] = 110;
1325 state->CH_Ctrl[13].bit[3] = 5;
1326 state->CH_Ctrl[13].val[3] = 0;
1327 state->CH_Ctrl[13].addr[4] = 110;
1328 state->CH_Ctrl[13].bit[4] = 6;
1329 state->CH_Ctrl[13].val[4] = 0;
1330 state->CH_Ctrl[13].addr[5] = 110;
1331 state->CH_Ctrl[13].bit[5] = 7;
1332 state->CH_Ctrl[13].val[5] = 1;
1334 state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1335 state->CH_Ctrl[14].size = 7 ;
1336 state->CH_Ctrl[14].addr[0] = 14;
1337 state->CH_Ctrl[14].bit[0] = 0;
1338 state->CH_Ctrl[14].val[0] = 0;
1339 state->CH_Ctrl[14].addr[1] = 14;
1340 state->CH_Ctrl[14].bit[1] = 1;
1341 state->CH_Ctrl[14].val[1] = 0;
1342 state->CH_Ctrl[14].addr[2] = 14;
1343 state->CH_Ctrl[14].bit[2] = 2;
1344 state->CH_Ctrl[14].val[2] = 0;
1345 state->CH_Ctrl[14].addr[3] = 14;
1346 state->CH_Ctrl[14].bit[3] = 3;
1347 state->CH_Ctrl[14].val[3] = 0;
1348 state->CH_Ctrl[14].addr[4] = 14;
1349 state->CH_Ctrl[14].bit[4] = 4;
1350 state->CH_Ctrl[14].val[4] = 0;
1351 state->CH_Ctrl[14].addr[5] = 14;
1352 state->CH_Ctrl[14].bit[5] = 5;
1353 state->CH_Ctrl[14].val[5] = 0;
1354 state->CH_Ctrl[14].addr[6] = 14;
1355 state->CH_Ctrl[14].bit[6] = 6;
1356 state->CH_Ctrl[14].val[6] = 0;
1358 state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1359 state->CH_Ctrl[15].size = 18 ;
1360 state->CH_Ctrl[15].addr[0] = 17;
1361 state->CH_Ctrl[15].bit[0] = 6;
1362 state->CH_Ctrl[15].val[0] = 0;
1363 state->CH_Ctrl[15].addr[1] = 17;
1364 state->CH_Ctrl[15].bit[1] = 7;
1365 state->CH_Ctrl[15].val[1] = 0;
1366 state->CH_Ctrl[15].addr[2] = 16;
1367 state->CH_Ctrl[15].bit[2] = 0;
1368 state->CH_Ctrl[15].val[2] = 0;
1369 state->CH_Ctrl[15].addr[3] = 16;
1370 state->CH_Ctrl[15].bit[3] = 1;
1371 state->CH_Ctrl[15].val[3] = 0;
1372 state->CH_Ctrl[15].addr[4] = 16;
1373 state->CH_Ctrl[15].bit[4] = 2;
1374 state->CH_Ctrl[15].val[4] = 0;
1375 state->CH_Ctrl[15].addr[5] = 16;
1376 state->CH_Ctrl[15].bit[5] = 3;
1377 state->CH_Ctrl[15].val[5] = 0;
1378 state->CH_Ctrl[15].addr[6] = 16;
1379 state->CH_Ctrl[15].bit[6] = 4;
1380 state->CH_Ctrl[15].val[6] = 0;
1381 state->CH_Ctrl[15].addr[7] = 16;
1382 state->CH_Ctrl[15].bit[7] = 5;
1383 state->CH_Ctrl[15].val[7] = 0;
1384 state->CH_Ctrl[15].addr[8] = 16;
1385 state->CH_Ctrl[15].bit[8] = 6;
1386 state->CH_Ctrl[15].val[8] = 0;
1387 state->CH_Ctrl[15].addr[9] = 16;
1388 state->CH_Ctrl[15].bit[9] = 7;
1389 state->CH_Ctrl[15].val[9] = 0;
1390 state->CH_Ctrl[15].addr[10] = 15;
1391 state->CH_Ctrl[15].bit[10] = 0;
1392 state->CH_Ctrl[15].val[10] = 0;
1393 state->CH_Ctrl[15].addr[11] = 15;
1394 state->CH_Ctrl[15].bit[11] = 1;
1395 state->CH_Ctrl[15].val[11] = 0;
1396 state->CH_Ctrl[15].addr[12] = 15;
1397 state->CH_Ctrl[15].bit[12] = 2;
1398 state->CH_Ctrl[15].val[12] = 0;
1399 state->CH_Ctrl[15].addr[13] = 15;
1400 state->CH_Ctrl[15].bit[13] = 3;
1401 state->CH_Ctrl[15].val[13] = 0;
1402 state->CH_Ctrl[15].addr[14] = 15;
1403 state->CH_Ctrl[15].bit[14] = 4;
1404 state->CH_Ctrl[15].val[14] = 0;
1405 state->CH_Ctrl[15].addr[15] = 15;
1406 state->CH_Ctrl[15].bit[15] = 5;
1407 state->CH_Ctrl[15].val[15] = 0;
1408 state->CH_Ctrl[15].addr[16] = 15;
1409 state->CH_Ctrl[15].bit[16] = 6;
1410 state->CH_Ctrl[15].val[16] = 1;
1411 state->CH_Ctrl[15].addr[17] = 15;
1412 state->CH_Ctrl[15].bit[17] = 7;
1413 state->CH_Ctrl[15].val[17] = 1;
1415 state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1416 state->CH_Ctrl[16].size = 5 ;
1417 state->CH_Ctrl[16].addr[0] = 112;
1418 state->CH_Ctrl[16].bit[0] = 0;
1419 state->CH_Ctrl[16].val[0] = 0;
1420 state->CH_Ctrl[16].addr[1] = 112;
1421 state->CH_Ctrl[16].bit[1] = 1;
1422 state->CH_Ctrl[16].val[1] = 0;
1423 state->CH_Ctrl[16].addr[2] = 112;
1424 state->CH_Ctrl[16].bit[2] = 2;
1425 state->CH_Ctrl[16].val[2] = 0;
1426 state->CH_Ctrl[16].addr[3] = 112;
1427 state->CH_Ctrl[16].bit[3] = 3;
1428 state->CH_Ctrl[16].val[3] = 0;
1429 state->CH_Ctrl[16].addr[4] = 112;
1430 state->CH_Ctrl[16].bit[4] = 4;
1431 state->CH_Ctrl[16].val[4] = 1;
1433 state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1434 state->CH_Ctrl[17].size = 1 ;
1435 state->CH_Ctrl[17].addr[0] = 14;
1436 state->CH_Ctrl[17].bit[0] = 7;
1437 state->CH_Ctrl[17].val[0] = 0;
1439 state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1440 state->CH_Ctrl[18].size = 4 ;
1441 state->CH_Ctrl[18].addr[0] = 107;
1442 state->CH_Ctrl[18].bit[0] = 3;
1443 state->CH_Ctrl[18].val[0] = 0;
1444 state->CH_Ctrl[18].addr[1] = 107;
1445 state->CH_Ctrl[18].bit[1] = 4;
1446 state->CH_Ctrl[18].val[1] = 0;
1447 state->CH_Ctrl[18].addr[2] = 107;
1448 state->CH_Ctrl[18].bit[2] = 5;
1449 state->CH_Ctrl[18].val[2] = 0;
1450 state->CH_Ctrl[18].addr[3] = 107;
1451 state->CH_Ctrl[18].bit[3] = 6;
1452 state->CH_Ctrl[18].val[3] = 0;
1454 state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1455 state->CH_Ctrl[19].size = 3 ;
1456 state->CH_Ctrl[19].addr[0] = 107;
1457 state->CH_Ctrl[19].bit[0] = 7;
1458 state->CH_Ctrl[19].val[0] = 1;
1459 state->CH_Ctrl[19].addr[1] = 106;
1460 state->CH_Ctrl[19].bit[1] = 0;
1461 state->CH_Ctrl[19].val[1] = 1;
1462 state->CH_Ctrl[19].addr[2] = 106;
1463 state->CH_Ctrl[19].bit[2] = 1;
1464 state->CH_Ctrl[19].val[2] = 1;
1466 state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1467 state->CH_Ctrl[20].size = 11 ;
1468 state->CH_Ctrl[20].addr[0] = 109;
1469 state->CH_Ctrl[20].bit[0] = 2;
1470 state->CH_Ctrl[20].val[0] = 0;
1471 state->CH_Ctrl[20].addr[1] = 109;
1472 state->CH_Ctrl[20].bit[1] = 3;
1473 state->CH_Ctrl[20].val[1] = 0;
1474 state->CH_Ctrl[20].addr[2] = 109;
1475 state->CH_Ctrl[20].bit[2] = 4;
1476 state->CH_Ctrl[20].val[2] = 0;
1477 state->CH_Ctrl[20].addr[3] = 109;
1478 state->CH_Ctrl[20].bit[3] = 5;
1479 state->CH_Ctrl[20].val[3] = 0;
1480 state->CH_Ctrl[20].addr[4] = 109;
1481 state->CH_Ctrl[20].bit[4] = 6;
1482 state->CH_Ctrl[20].val[4] = 0;
1483 state->CH_Ctrl[20].addr[5] = 109;
1484 state->CH_Ctrl[20].bit[5] = 7;
1485 state->CH_Ctrl[20].val[5] = 0;
1486 state->CH_Ctrl[20].addr[6] = 108;
1487 state->CH_Ctrl[20].bit[6] = 0;
1488 state->CH_Ctrl[20].val[6] = 0;
1489 state->CH_Ctrl[20].addr[7] = 108;
1490 state->CH_Ctrl[20].bit[7] = 1;
1491 state->CH_Ctrl[20].val[7] = 0;
1492 state->CH_Ctrl[20].addr[8] = 108;
1493 state->CH_Ctrl[20].bit[8] = 2;
1494 state->CH_Ctrl[20].val[8] = 1;
1495 state->CH_Ctrl[20].addr[9] = 108;
1496 state->CH_Ctrl[20].bit[9] = 3;
1497 state->CH_Ctrl[20].val[9] = 1;
1498 state->CH_Ctrl[20].addr[10] = 108;
1499 state->CH_Ctrl[20].bit[10] = 4;
1500 state->CH_Ctrl[20].val[10] = 1;
1502 state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1503 state->CH_Ctrl[21].size = 6 ;
1504 state->CH_Ctrl[21].addr[0] = 106;
1505 state->CH_Ctrl[21].bit[0] = 2;
1506 state->CH_Ctrl[21].val[0] = 0;
1507 state->CH_Ctrl[21].addr[1] = 106;
1508 state->CH_Ctrl[21].bit[1] = 3;
1509 state->CH_Ctrl[21].val[1] = 0;
1510 state->CH_Ctrl[21].addr[2] = 106;
1511 state->CH_Ctrl[21].bit[2] = 4;
1512 state->CH_Ctrl[21].val[2] = 0;
1513 state->CH_Ctrl[21].addr[3] = 106;
1514 state->CH_Ctrl[21].bit[3] = 5;
1515 state->CH_Ctrl[21].val[3] = 0;
1516 state->CH_Ctrl[21].addr[4] = 106;
1517 state->CH_Ctrl[21].bit[4] = 6;
1518 state->CH_Ctrl[21].val[4] = 0;
1519 state->CH_Ctrl[21].addr[5] = 106;
1520 state->CH_Ctrl[21].bit[5] = 7;
1521 state->CH_Ctrl[21].val[5] = 1;
1523 state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1524 state->CH_Ctrl[22].size = 1 ;
1525 state->CH_Ctrl[22].addr[0] = 138;
1526 state->CH_Ctrl[22].bit[0] = 4;
1527 state->CH_Ctrl[22].val[0] = 1;
1529 state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1530 state->CH_Ctrl[23].size = 1 ;
1531 state->CH_Ctrl[23].addr[0] = 17;
1532 state->CH_Ctrl[23].bit[0] = 5;
1533 state->CH_Ctrl[23].val[0] = 0;
1535 state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1536 state->CH_Ctrl[24].size = 1 ;
1537 state->CH_Ctrl[24].addr[0] = 111;
1538 state->CH_Ctrl[24].bit[0] = 3;
1539 state->CH_Ctrl[24].val[0] = 0;
1541 state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1542 state->CH_Ctrl[25].size = 1 ;
1543 state->CH_Ctrl[25].addr[0] = 112;
1544 state->CH_Ctrl[25].bit[0] = 7;
1545 state->CH_Ctrl[25].val[0] = 0;
1547 state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1548 state->CH_Ctrl[26].size = 1 ;
1549 state->CH_Ctrl[26].addr[0] = 136;
1550 state->CH_Ctrl[26].bit[0] = 7;
1551 state->CH_Ctrl[26].val[0] = 0;
1553 state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1554 state->CH_Ctrl[27].size = 1 ;
1555 state->CH_Ctrl[27].addr[0] = 149;
1556 state->CH_Ctrl[27].bit[0] = 7;
1557 state->CH_Ctrl[27].val[0] = 0;
1559 state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1560 state->CH_Ctrl[28].size = 1 ;
1561 state->CH_Ctrl[28].addr[0] = 149;
1562 state->CH_Ctrl[28].bit[0] = 6;
1563 state->CH_Ctrl[28].val[0] = 0;
1565 state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1566 state->CH_Ctrl[29].size = 1 ;
1567 state->CH_Ctrl[29].addr[0] = 149;
1568 state->CH_Ctrl[29].bit[0] = 5;
1569 state->CH_Ctrl[29].val[0] = 1;
1571 state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1572 state->CH_Ctrl[30].size = 1 ;
1573 state->CH_Ctrl[30].addr[0] = 149;
1574 state->CH_Ctrl[30].bit[0] = 4;
1575 state->CH_Ctrl[30].val[0] = 1;
1577 state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1578 state->CH_Ctrl[31].size = 1 ;
1579 state->CH_Ctrl[31].addr[0] = 149;
1580 state->CH_Ctrl[31].bit[0] = 3;
1581 state->CH_Ctrl[31].val[0] = 0;
1583 state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1584 state->CH_Ctrl[32].size = 1 ;
1585 state->CH_Ctrl[32].addr[0] = 93;
1586 state->CH_Ctrl[32].bit[0] = 1;
1587 state->CH_Ctrl[32].val[0] = 0;
1589 state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1590 state->CH_Ctrl[33].size = 1 ;
1591 state->CH_Ctrl[33].addr[0] = 93;
1592 state->CH_Ctrl[33].bit[0] = 0;
1593 state->CH_Ctrl[33].val[0] = 0;
1595 state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1596 state->CH_Ctrl[34].size = 6 ;
1597 state->CH_Ctrl[34].addr[0] = 92;
1598 state->CH_Ctrl[34].bit[0] = 2;
1599 state->CH_Ctrl[34].val[0] = 0;
1600 state->CH_Ctrl[34].addr[1] = 92;
1601 state->CH_Ctrl[34].bit[1] = 3;
1602 state->CH_Ctrl[34].val[1] = 0;
1603 state->CH_Ctrl[34].addr[2] = 92;
1604 state->CH_Ctrl[34].bit[2] = 4;
1605 state->CH_Ctrl[34].val[2] = 0;
1606 state->CH_Ctrl[34].addr[3] = 92;
1607 state->CH_Ctrl[34].bit[3] = 5;
1608 state->CH_Ctrl[34].val[3] = 0;
1609 state->CH_Ctrl[34].addr[4] = 92;
1610 state->CH_Ctrl[34].bit[4] = 6;
1611 state->CH_Ctrl[34].val[4] = 0;
1612 state->CH_Ctrl[34].addr[5] = 92;
1613 state->CH_Ctrl[34].bit[5] = 7;
1614 state->CH_Ctrl[34].val[5] = 0;
1616 state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1617 state->CH_Ctrl[35].size = 6 ;
1618 state->CH_Ctrl[35].addr[0] = 93;
1619 state->CH_Ctrl[35].bit[0] = 2;
1620 state->CH_Ctrl[35].val[0] = 0;
1621 state->CH_Ctrl[35].addr[1] = 93;
1622 state->CH_Ctrl[35].bit[1] = 3;
1623 state->CH_Ctrl[35].val[1] = 0;
1624 state->CH_Ctrl[35].addr[2] = 93;
1625 state->CH_Ctrl[35].bit[2] = 4;
1626 state->CH_Ctrl[35].val[2] = 0;
1627 state->CH_Ctrl[35].addr[3] = 93;
1628 state->CH_Ctrl[35].bit[3] = 5;
1629 state->CH_Ctrl[35].val[3] = 0;
1630 state->CH_Ctrl[35].addr[4] = 93;
1631 state->CH_Ctrl[35].bit[4] = 6;
1632 state->CH_Ctrl[35].val[4] = 0;
1633 state->CH_Ctrl[35].addr[5] = 93;
1634 state->CH_Ctrl[35].bit[5] = 7;
1635 state->CH_Ctrl[35].val[5] = 0;
1638 state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1639 state->CH_Ctrl[36].size = 1 ;
1640 state->CH_Ctrl[36].addr[0] = 109;
1641 state->CH_Ctrl[36].bit[0] = 1;
1642 state->CH_Ctrl[36].val[0] = 1;
1644 state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1645 state->CH_Ctrl[37].size = 2 ;
1646 state->CH_Ctrl[37].addr[0] = 112;
1647 state->CH_Ctrl[37].bit[0] = 5;
1648 state->CH_Ctrl[37].val[0] = 0;
1649 state->CH_Ctrl[37].addr[1] = 112;
1650 state->CH_Ctrl[37].bit[1] = 6;
1651 state->CH_Ctrl[37].val[1] = 0;
1653 state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1654 state->CH_Ctrl[38].size = 1 ;
1655 state->CH_Ctrl[38].addr[0] = 65;
1656 state->CH_Ctrl[38].bit[0] = 1;
1657 state->CH_Ctrl[38].val[0] = 0;
1695 struct mxl5005s_state *state = fe->tuner_priv;
1698 state->Mode = Mode;
1699 state->IF_Mode = IF_mode;
1700 state->Chan_Bandwidth = Bandwidth;
1701 state->IF_OUT = IF_out;
1702 state->Fxtal = Fxtal;
1703 state->AGC_Mode = AGC_Mode;
1704 state->TOP = TOP;
1705 state->IF_OUT_LOAD = IF_OUT_LOAD;
1706 state->CLOCK_OUT = CLOCK_OUT;
1707 state->DIV_OUT = DIV_OUT;
1708 state->CAPSELECT = CAPSELECT;
1709 state->EN_RSSI = EN_RSSI;
1710 state->Mod_Type = Mod_Type;
1711 state->TF_Type = TF_Type;
1724 struct mxl5005s_state *state = fe->tuner_priv;
1725 if (state->Mode == 1) /* Digital Mode */
1726 state->IF_LO = state->IF_OUT;
1728 if (state->IF_Mode == 0) /* Analog Zero IF mode */
1729 state->IF_LO = state->IF_OUT + 400000;
1731 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1737 struct mxl5005s_state *state = fe->tuner_priv;
1739 if (state->Mode == 1) /* Digital Mode */ {
1741 state->RF_LO = state->RF_IN;
1743 state->TG_LO = state->RF_IN - 750000;
1745 if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
1746 state->RF_LO = state->RF_IN - 400000;
1747 state->TG_LO = state->RF_IN - 1750000;
1749 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1750 state->TG_LO = state->RF_IN -
1751 state->Chan_Bandwidth + 500000;
1770 struct mxl5005s_state *state = fe->tuner_priv;
1776 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1779 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1780 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1781 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1782 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1786 if (state->Mode) { /* Digital Mode */
1787 switch (state->Chan_Bandwidth) {
1800 switch (state->Chan_Bandwidth) {
1803 (state->IF_Mode ? 0 : 3));
1807 (state->IF_Mode ? 1 : 4));
1811 (state->IF_Mode ? 2 : 5));
1817 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1819 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1820 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1823 if (state->AGC_Mode == 0) /* Dual AGC */ {
1827 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1829 if (state->TOP == 55) /* TOP == 5.5 */
1832 if (state->TOP == 72) /* TOP == 7.2 */
1835 if (state->TOP == 92) /* TOP == 9.2 */
1838 if (state->TOP == 110) /* TOP == 11.0 */
1841 if (state->TOP == 129) /* TOP == 12.9 */
1844 if (state->TOP == 147) /* TOP == 14.7 */
1847 if (state->TOP == 168) /* TOP == 16.8 */
1850 if (state->TOP == 194) /* TOP == 19.4 */
1853 if (state->TOP == 212) /* TOP == 21.2 */
1856 if (state->TOP == 232) /* TOP == 23.2 */
1859 if (state->TOP == 252) /* TOP == 25.2 */
1862 if (state->TOP == 271) /* TOP == 27.1 */
1865 if (state->TOP == 292) /* TOP == 29.2 */
1868 if (state->TOP == 317) /* TOP == 31.7 */
1871 if (state->TOP == 349) /* TOP == 34.9 */
1878 if (state->IF_OUT_LOAD == 200) {
1882 if (state->IF_OUT_LOAD == 300) {
1890 if (state->Mode) { /* Digital Mode */
1891 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
1897 if ((state->IF_OUT == 36125000UL) ||
1898 (state->IF_OUT == 36150000UL)) {
1904 if (state->IF_OUT > 36150000UL) {
1911 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
1917 if (state->IF_OUT > 5000000UL) {
1926 if (state->CLOCK_OUT)
1931 if (state->DIV_OUT == 1)
1933 if (state->DIV_OUT == 0)
1937 if (state->CAPSELECT)
1942 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
1944 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
1947 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
1949 if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
1953 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
1962 MXL_Ceiling(state->Fxtal, 1000000));
1967 if (state->EN_RSSI) {
1986 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
1987 state->AGC_Mode = 1; /* Single AGC Mode */
2003 if (state->IF_OUT <= 6280000UL) /* Low IF */
2009 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
2010 state->AGC_Mode = 1; /* Single AGC Mode */
2030 if (state->IF_OUT <= 6280000UL) /* Low IF */
2035 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
2036 state->Mode = MXL_DIGITAL_MODE;
2038 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2053 if (state->IF_OUT <= 6280000UL) /* Low IF */
2060 if (state->Mod_Type == MXL_ANALOG_CABLE) {
2062 /* state->Mode = MXL_DIGITAL_MODE; */
2064 state->AGC_Mode = 1; /* Single AGC Mode */
2077 if (state->Mod_Type == MXL_ANALOG_OTA) {
2079 /* state->Mode = MXL_ANALOG_MODE; */
2096 if (state->EN_RSSI == 0) {
2108 struct mxl5005s_state *state = fe->tuner_priv;
2115 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2117 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2121 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
2122 if (state->IF_LO == 41000000UL) {
2127 if (state->IF_LO == 47000000UL) {
2132 if (state->IF_LO == 54000000UL) {
2137 if (state->IF_LO == 60000000UL) {
2142 if (state->IF_LO == 39250000UL) {
2147 if (state->IF_LO == 39650000UL) {
2152 if (state->IF_LO == 40150000UL) {
2157 if (state->IF_LO == 40650000UL) {
2164 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
2165 if (state->IF_LO == 57000000UL) {
2170 if (state->IF_LO == 44000000UL) {
2175 if (state->IF_LO == 43750000UL) {
2180 if (state->IF_LO == 36650000UL) {
2185 if (state->IF_LO == 36150000UL) {
2190 if (state->IF_LO == 36000000UL) {
2195 if (state->IF_LO == 35250000UL) {
2200 if (state->IF_LO == 34750000UL) {
2205 if (state->IF_LO == 6280000UL) {
2210 if (state->IF_LO == 5000000UL) {
2215 if (state->IF_LO == 4500000UL) {
2220 if (state->IF_LO == 4570000UL) {
2225 if (state->IF_LO == 4000000UL) {
2230 if (state->IF_LO == 57400000UL) {
2235 if (state->IF_LO == 44400000UL) {
2240 if (state->IF_LO == 44150000UL) {
2245 if (state->IF_LO == 37050000UL) {
2250 if (state->IF_LO == 36550000UL) {
2255 if (state->IF_LO == 36125000UL) {
2260 if (state->IF_LO == 6000000UL) {
2265 if (state->IF_LO == 5400000UL) {
2270 if (state->IF_LO == 5380000UL) {
2275 if (state->IF_LO == 5200000UL) {
2280 if (state->IF_LO == 4900000UL) {
2285 if (state->IF_LO == 4400000UL) {
2290 if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ {
2298 intModVal = Fref / (state->Fxtal * Kdbl/2);
2301 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
2304 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
2320 struct mxl5005s_state *state = fe->tuner_priv;
2332 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2334 state->RF_IN = RF_Freq;
2338 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2340 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2352 if (state->RF_LO < 40000000UL)
2355 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2362 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2369 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2376 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2383 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2390 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2397 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2404 if (state->RF_LO > 900000000UL)
2409 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2413 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2417 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2421 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2425 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2429 if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2433 if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2437 if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2441 if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2445 if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2449 if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2453 if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2457 if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2461 if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2465 if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2469 if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2489 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2502 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2515 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2528 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2541 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2554 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2567 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2580 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2593 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2606 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2619 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2637 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2641 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
2645 E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
2646 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
2647 (2*state->Fxtal*Kdbl_RF/10000);
2652 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2672 if (state->TG_LO < 33000000UL)
2677 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2686 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2695 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2704 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2713 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2722 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2731 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2740 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2749 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2758 tg_divval = (state->TG_LO*divider_val/100000) *
2759 (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
2760 (state->Fxtal/1000);
2764 if (state->TG_LO > 600000000UL)
2774 Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
2777 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
2783 * ((state->TG_LO/10000)*divider_val *
2784 * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
2791 if (state->Mod_Type == MXL_QAM) {
2792 if (state->config->qam_gain != 0)
2794 state->config->qam_gain);
2795 else if (state->RF_IN < 680000000)
2802 if (state->TF_Type == MXL_TF_OFF) {
2811 if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
2815 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2822 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2829 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2836 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2843 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2850 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2857 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2864 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2871 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2880 if (state->TF_Type == MXL_TF_C_H) {
2885 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2891 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2897 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2903 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2909 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2915 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2921 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2927 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2933 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2941 if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
2945 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
2951 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
2957 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
2963 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
2969 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
2975 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
2981 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
2989 if (state->TF_Type == MXL_TF_D_L) {
2995 if (state->RF_IN >= 471000000 &&
2996 (state->RF_IN - 471000000)%6000000 != 0) {
3005 if (state->RF_IN >= 43000000 &&
3006 state->RF_IN < 140000000) {
3013 if (state->RF_IN >= 140000000 &&
3014 state->RF_IN < 240000000) {
3020 if (state->RF_IN >= 240000000 &&
3021 state->RF_IN < 340000000) {
3027 if (state->RF_IN >= 340000000 &&
3028 state->RF_IN < 430000000) {
3034 if (state->RF_IN >= 430000000 &&
3035 state->RF_IN < 470000000) {
3041 if (state->RF_IN >= 470000000 &&
3042 state->RF_IN < 570000000) {
3048 if (state->RF_IN >= 570000000 &&
3049 state->RF_IN < 620000000) {
3055 if (state->RF_IN >= 620000000 &&
3056 state->RF_IN < 760000000) {
3062 if (state->RF_IN >= 760000000 &&
3063 state->RF_IN <= 900000000) {
3072 if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
3076 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3082 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3088 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3094 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3100 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3106 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3112 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3120 if (state->TF_Type == MXL_TF_F) {
3125 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
3131 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
3137 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
3143 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
3149 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
3155 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
3161 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
3169 if (state->TF_Type == MXL_TF_E_2) {
3174 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3180 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3186 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3192 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3198 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3204 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3210 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3218 if (state->TF_Type == MXL_TF_G) {
3223 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
3230 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
3236 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
3242 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3248 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
3254 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3260 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
3266 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
3274 if (state->TF_Type == MXL_TF_E_NA) {
3280 if (state->RF_IN >= 471000000 &&
3281 (state->RF_IN - 471000000)%6000000 != 0) {
3313 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3320 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3326 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3332 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3338 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3344 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3350 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3379 if (GPIO_Val == 3) { /* tri-state */
3393 if (GPIO_Val == 3) { /* tri-state */
3421 struct mxl5005s_state *state = fe->tuner_priv;
3428 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3430 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3432 highLimit = 1 << state->Init_Ctrl[i].size;
3434 for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3435 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3436 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3437 (u8)(state->Init_Ctrl[i].bit[j]),
3441 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3442 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3450 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3452 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3454 highLimit = 1 << state->CH_Ctrl[i].size;
3456 for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3457 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3458 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3459 (u8)(state->CH_Ctrl[i].bit[j]),
3463 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3464 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3473 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3475 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3477 highLimit = (1 << state->MXL_Ctrl[i].size);
3479 for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3480 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3481 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3482 (u8)(state->MXL_Ctrl[i].bit[j]),
3486 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3487 ctrlVal += state->
3501 struct mxl5005s_state *state = fe->tuner_priv;
3505 if (RegNum == state->TunerRegs[i].Reg_Num) {
3506 *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3516 struct mxl5005s_state *state = fe->tuner_priv;
3520 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3522 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3525 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3526 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
3532 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3534 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3537 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3538 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3546 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3548 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3551 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3552 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
3565 struct mxl5005s_state *state = fe->tuner_priv;
3576 for (i = 0; i < state->TunerRegs_Num; i++) {
3577 if (state->TunerRegs[i].Reg_Num == address) {
3579 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
3581 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
3664 static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
3666 if (state == 1) /* Load_Start */
3668 if (state == 2) /* Power_Down */
3670 if (state == 3) /* Synth_Reset */
3672 if (state == 4) /* Seq_Off */
3681 struct mxl5005s_state *state = fe->tuner_priv;
3692 if (state->Mode == 0 && state->IF_Mode == 1) {
3700 if (state->Mode == 0 && state->IF_Mode == 0) {
3708 if (state->Mode == 1) /* Digital Mode */ {
3728 if (state->Mode == 0 && state->IF_Mode == 1) {
3736 if (state->Mode == 0 && state->IF_Mode == 0) {
3744 if (state->Mode == 1) /* Digital Mode */ {
3764 if (state->Mode == 0 && state->IF_Mode == 1) {
3772 if (state->Mode == 0 && state->IF_Mode == 0) {
3780 if (state->Mode == 1) /* Digital Mode */ {
3800 if (state->Mode == 0 && state->IF_Mode == 1) {
3808 if (state->Mode == 0 && state->IF_Mode == 0) {
3816 if (state->Mode == 1) /* Digital Mode */ {
3830 struct mxl5005s_state *state = fe->tuner_priv;
3849 struct mxl5005s_state *state = fe->tuner_priv;
3853 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3861 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3877 struct mxl5005s_state *state = fe->tuner_priv;
3879 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3887 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3918 struct mxl5005s_state *state = fe->tuner_priv;
3921 state->current_mode = MXL_QAM;
3928 struct mxl5005s_state *state = fe->tuner_priv;
3941 ByteTable[0] |= state->config->AgcMasterByte;
3958 struct mxl5005s_state *state = fe->tuner_priv;
3959 struct mxl5005s_config *c = state->config;
3987 struct mxl5005s_state *state = fe->tuner_priv;
4007 if (req_mode != state->current_mode) {
4030 state->current_mode = req_mode;
4046 struct mxl5005s_state *state = fe->tuner_priv;
4049 *frequency = state->RF_IN;
4056 struct mxl5005s_state *state = fe->tuner_priv;
4059 *bandwidth = state->Chan_Bandwidth;
4092 struct mxl5005s_state *state = NULL;
4095 state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4096 if (state == NULL)
4099 state->frontend = fe;
4100 state->config = config;
4101 state->i2c = i2c;
4109 fe->tuner_priv = state;