Lines Matching defs:Write_hfc
62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
153 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
193 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
314 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
315 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */
317 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */
352 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
356 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */
358 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
368 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
370 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */
372 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */
376 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
380 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
385 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */
387 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */
390 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
392 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
394 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
404 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
405 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
406 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
407 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
408 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
412 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
602 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */
605 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */
607 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */
609 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION);
637 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
638 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
639 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
640 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
641 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
642 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
734 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
944 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */
946 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */
948 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
949 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
955 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
961 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
967 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
974 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */
975 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */
977 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
980 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */
981 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */
983 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
992 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
1124 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1125 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1126 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
1127 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
1128 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1129 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1286 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1290 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1292 Write_hfc(cs, HFCSX_STATES, 4);
1296 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1299 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1300 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1302 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */
1312 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1371 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1373 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1492 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1493 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);