Lines Matching refs:cfg
113 struct _iohandle cfg;
285 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL);
303 val = readb(hw->cfg.p);
310 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */
322 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS);
340 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR);
358 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
363 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
409 writel(PITA_INT0_ENABLE, hw->cfg.p);
413 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
416 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
419 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
422 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
424 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
427 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
429 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
433 (u32)hw->cfg.start + GAZEL_INCSR);
437 (u32)hw->cfg.start + GAZEL_INCSR);
453 writel(0, hw->cfg.p);
457 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
460 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
463 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
466 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
468 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
471 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
473 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
477 outb(0, (u32)hw->cfg.start + GAZEL_INCSR);
506 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL);
508 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL);
510 outb(9, (u32)hw->cfg.start + 0x69);
512 (u32)hw->cfg.start + DIVA_PCI_CTRL);
516 hw->cfg.p + PITA_MISC_REG);
518 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG);
523 hw->cfg.p + PITA_MISC_REG);
526 hw->cfg.p + PITA_MISC_REG);
546 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
548 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
550 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
552 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
556 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
558 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
561 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
568 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
570 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
573 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
645 if (hw->cfg.mode) {
646 if (hw->cfg.p) {
647 release_mem_region(hw->cfg.start, hw->cfg.size);
648 iounmap(hw->cfg.p);
650 release_region(hw->cfg.start, hw->cfg.size);
651 hw->cfg.mode = AM_NONE;
669 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar);
670 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar);
672 if (!request_mem_region(hw->cfg.start, hw->cfg.size,
676 if (!request_region(hw->cfg.start, hw->cfg.size,
683 (ulong)hw->cfg.start, (ulong)hw->cfg.size);
687 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size);
688 hw->cfg.mode = hw->ci->cfg_mode;
690 pr_notice("%s: IO cfg %lx (%lu bytes) mode%d\n",
691 hw->name, (ulong)hw->cfg.start,
692 (ulong)hw->cfg.size, hw->ci->cfg_mode);
727 hw->isac.mode = hw->cfg.mode;
728 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE;
729 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT;
730 hw->hscx.mode = hw->cfg.mode;
731 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE;
732 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT;
753 hw->isac.mode = hw->cfg.mode;
754 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
755 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
756 hw->hscx.mode = hw->cfg.mode;
757 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
758 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
759 outb(0xff, (ulong)hw->cfg.start);
761 outb(0x00, (ulong)hw->cfg.start);
763 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL);