Lines Matching defs:dslot
106 * dslot:
107 * NOTE: only one dslot value must be given for every card.
205 static int dslot[MAX_CARDS];
233 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
1616 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1617 if (hc->chan[hc->dslot].dch->dev.D.protocol
2425 dch = hc->chan[hc->dslot].dch;
2426 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2429 if (!temp && hc->chan[hc->dslot].los)
2432 if (temp && !hc->chan[hc->dslot].los)
2435 hc->chan[hc->dslot].los = temp;
2437 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2440 if (!temp && hc->chan[hc->dslot].ais)
2443 if (temp && !hc->chan[hc->dslot].ais)
2446 hc->chan[hc->dslot].ais = temp;
2448 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2451 if (!temp && hc->chan[hc->dslot].slip_rx)
2454 hc->chan[hc->dslot].slip_rx = temp;
2456 if (!temp && hc->chan[hc->dslot].slip_tx)
2459 hc->chan[hc->dslot].slip_tx = temp;
2461 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2464 if (!temp && hc->chan[hc->dslot].rdi)
2467 if (temp && !hc->chan[hc->dslot].rdi)
2470 hc->chan[hc->dslot].rdi = temp;
2473 switch (hc->chan[hc->dslot].sync) {
2482 hc->chan[hc->dslot].jitter | V_RX_INIT);
2484 hc->chan[hc->dslot].jitter | V_RX_INIT);
2485 hc->chan[hc->dslot].sync = 1;
2496 hc->chan[hc->dslot].sync = 0;
2507 hc->chan[hc->dslot].sync = 2;
2517 hc->chan[hc->dslot].sync = 0;
2527 hc->chan[hc->dslot].sync = 1;
2743 dch = hc->chan[hc->dslot].dch;
3835 hc->chan[hc->dslot].slot_tx = -1;
3836 hc->chan[hc->dslot].slot_rx = -1;
3837 hc->chan[hc->dslot].conf = -1;
3838 if (hc->dslot) {
3839 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3846 if (i == hc->dslot)
3854 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3858 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3871 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3876 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
4681 dch->dev.nrbchan = (hc->dslot) ? 30 : 31;
4682 dch->slot = hc->dslot;
4683 hc->chan[hc->dslot].dch = dch;
4684 hc->chan[hc->dslot].port = 0;
4685 hc->chan[hc->dslot].nt_timer = -1;
4687 if (ch == hc->dslot) /* skip dchannel */
4732 &hc->chan[hc->dslot].cfg);
4742 &hc->chan[hc->dslot].cfg);
4751 &hc->chan[hc->dslot].cfg);
4761 &hc->chan[hc->dslot].cfg);
4771 &hc->chan[hc->dslot].cfg);
4780 &hc->chan[hc->dslot].cfg);
4812 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4817 __func__, hc->chan[hc->dslot].jitter,
4820 hc->chan[hc->dslot].jitter = 2; /* default */
4992 if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) {
4993 hc->dslot = 0;
4997 if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32
4999 hc->dslot = dslot[HFC_cnt];
5001 "time slot %d\n", dslot[HFC_cnt]);
5003 hc->dslot = 16;