Lines Matching refs:ohci
137 printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
148 printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
158 static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
163 static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
205 static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
211 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
213 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
216 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
222 r = reg_read(ohci, OHCI1394_PhyControl);
228 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
233 static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
239 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
241 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
244 r = reg_read(ohci, OHCI1394_PhyControl);
255 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
261 static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
265 old = get_phy_reg (ohci, addr);
267 set_phy_reg (ohci, addr, old);
272 static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
275 quadlet_t *q = ohci->selfid_buf_cpu;
276 quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
282 if (ohci->selfid_swap)
291 self_id_count, q0, ohci->self_id_errors);
295 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
296 set_phy_reg_mask (ohci, 1, 0x40);
297 ohci->self_id_errors++;
306 ohci->self_id_errors = 0;
312 if (ohci->selfid_swap) {
338 static void ohci_soft_reset(struct ti_ohci *ohci) {
341 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
344 if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset))
355 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
358 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
387 reg_write(ohci, d->ctrlClear, 0xffffffff);
390 reg_write(ohci, d->ctrlSet, 0xd0000000);
393 reg_write(ohci, d->ctxtMatch, 0xf0000000);
396 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
397 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
400 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
404 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
407 reg_write(ohci, d->ctrlSet, 0x00008000);
415 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
418 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
429 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
436 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
440 reg_write(ohci, reg, 0xffffffff);
441 tmp = reg_read(ohci, reg);
450 static void ohci_initialize(struct ti_ohci *ohci)
455 spin_lock_init(&ohci->phy_reg_lock);
458 buf = reg_read(ohci, OHCI1394_BusOptions);
466 reg_write(ohci, OHCI1394_BusOptions, buf);
469 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
472 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
475 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
479 reg_write(ohci, OHCI1394_LinkControlSet,
482 i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;
487 set_phy_reg(ohci, 4, i);
490 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
493 reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID);
496 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
499 ohci->max_packet_size =
500 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
503 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
504 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
507 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
508 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
511 initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);
512 initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);
515 initialize_dma_trm_ctx(&ohci->at_req_context);
516 initialize_dma_trm_ctx(&ohci->at_resp_context);
519 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
527 reg_write(ohci, OHCI1394_PhyUpperBound,
531 reg_read(ohci, OHCI1394_PhyUpperBound));
534 reg_write(ohci, OHCI1394_ATRetries,
540 reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
543 reg_write(ohci, OHCI1394_IntMaskSet,
559 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
561 buf = reg_read(ohci, OHCI1394_Version);
565 ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), ohci->dev->irq,
566 (unsigned long long)pci_resource_start(ohci->dev, 0),
567 (unsigned long long)pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
568 ohci->max_packet_size,
569 ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx);
573 num_ports = get_phy_reg(ohci, 2) & 0xf;
577 set_phy_reg(ohci, 7, i);
578 status = get_phy_reg(ohci, 8);
581 set_phy_reg(ohci, 8, status & ~1);
585 if ((ohci->max_packet_size < 512) ||
586 (ohci->max_packet_size > 4096)) {
596 reg_write(ohci, OHCI1394_BusOptions,
597 (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);
598 ohci->max_packet_size = 512;
601 (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);
602 reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
606 (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)
610 reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
612 (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);
618 static void insert_packet(struct ti_ohci *ohci,
626 NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel,
637 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
687 pci_map_single(ohci->dev, packet->data,
737 pci_map_single(ohci->dev, packet->data,
776 static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
793 insert_packet(ohci, d, packet);
802 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
803 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
806 reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
812 reg_write(ohci, d->ctrlSet, 0x8000);
815 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
819 reg_write(ohci, d->ctrlSet, 0x1000);
828 struct ti_ohci *ohci = host->hostdata;
832 if (packet->data_size > ohci->max_packet_size) {
840 d = &ohci->at_req_context;
842 d = &ohci->at_resp_context;
844 d = &ohci->at_req_context;
850 dma_trm_flush(ohci, d);
859 struct ti_ohci *ohci = host->hostdata;
866 phy_reg = get_phy_reg(ohci, 5);
868 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
871 phy_reg = get_phy_reg(ohci, 1);
873 set_phy_reg(ohci, 1, phy_reg); /* set IBR */
876 phy_reg = get_phy_reg(ohci, 1);
879 set_phy_reg(ohci, 1, phy_reg); /* clear RHB */
882 phy_reg = get_phy_reg(ohci, 5);
884 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
887 phy_reg = get_phy_reg(ohci, 1);
890 set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */
893 phy_reg = get_phy_reg(ohci, 1);
896 set_phy_reg(ohci, 1, phy_reg); /* set RHB */
899 phy_reg = get_phy_reg(ohci, 5);
901 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
904 phy_reg = get_phy_reg(ohci, 1);
906 set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */
914 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
918 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
928 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
934 reg_write(ohci, OHCI1394_LinkControlSet,
940 reg_write(ohci, OHCI1394_LinkControlClear,
949 dma_trm_reset(&ohci->at_req_context);
950 dma_trm_reset(&ohci->at_resp_context);
979 struct ti_ohci *ohci;
1028 struct ti_ohci *ohci = iso->host->hostdata;
1038 recv->ohci = ohci;
1110 recv->ohci->dev))
1120 if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) {
1136 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF);
1137 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF);
1162 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context);
1165 ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL);
1174 ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task);
1250 reg_write(recv->ohci, reg, (1 << i));
1254 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1265 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i));
1267 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32)));
1270 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i));
1272 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32)));
1278 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1284 struct ti_ohci *ohci = recv->ohci;
1287 reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF);
1296 reg_write(recv->ohci, recv->ContextControlSet, command);
1303 reg_write(recv->ohci, recv->ContextControlSet, (1 << 28));
1313 reg_write(recv->ohci, recv->ContextControlSet, (1 << 29));
1320 seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
1339 reg_write(recv->ohci, recv->ContextMatch, contextMatch);
1346 reg_write(recv->ohci, recv->CommandPtr, command);
1349 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context);
1354 reg_write(recv->ohci, recv->ContextControlSet, 0x8000);
1359 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1362 if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) {
1365 reg_read(recv->ohci, recv->ContextControlSet));
1407 reg_write(recv->ohci, recv->ContextControlSet, (1 << 12));
1439 struct ti_ohci *ohci = recv->ohci;
1545 struct ti_ohci *ohci = recv->ohci;
1604 struct ti_ohci *ohci = recv->ohci;
1693 struct ti_ohci *ohci;
1733 xmit->ohci = iso->host->hostdata;
1742 if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev))
1748 if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) {
1771 struct ti_ohci *ohci = xmit->ohci;
1774 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context);
1777 if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) {
1790 ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task);
1803 struct ti_ohci *ohci = xmit->ohci;
1867 struct ti_ohci *ohci = xmit->ohci;
1960 reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12);
1965 reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer);
1973 struct ti_ohci *ohci = xmit->ohci;
1976 reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF);
1980 reg_write(xmit->ohci, xmit->CommandPtr,
1989 u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
1996 reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16));
2000 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context);
2003 reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000);
2010 if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) {
2012 reg_read(xmit->ohci, xmit->ContextControlSet));
2085 struct ti_ohci *ohci = d->ohci;
2088 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
2114 hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED);
2118 static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci,
2126 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
2128 list_for_each_entry(t, &ohci->iso_tasklet_list, link) {
2141 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
2147 struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
2148 struct hpsb_host *host = ohci->host;
2155 spin_lock_irqsave(&ohci->event_lock, flags);
2156 event = reg_read(ohci, OHCI1394_IntEventClear);
2157 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
2158 spin_unlock_irqrestore(&ohci->event_lock, flags);
2177 if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800)
2180 reg_read(ohci, OHCI1394_AsReqTrContextControlSet),
2181 reg_read(ohci, OHCI1394_AsReqTrCommandPtr));
2183 if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800)
2186 reg_read(ohci, OHCI1394_AsRspTrContextControlSet),
2187 reg_read(ohci, OHCI1394_AsRspTrCommandPtr));
2189 if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800)
2192 reg_read(ohci, OHCI1394_AsReqRcvContextControlSet),
2193 reg_read(ohci, OHCI1394_AsReqRcvCommandPtr));
2195 if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800)
2198 reg_read(ohci, OHCI1394_AsRspRcvContextControlSet),
2199 reg_read(ohci, OHCI1394_AsRspRcvCommandPtr));
2201 for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) {
2202 if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800)
2205 reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)),
2206 reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx)));
2209 for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) {
2210 if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800)
2213 reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)),
2214 reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)),
2215 reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx)));
2230 reg_write(ohci, OHCI1394_LinkControlSet,
2245 spin_lock_irqsave(&ohci->event_lock, flags);
2246 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2248 if (ohci->check_busreset) {
2253 while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
2254 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2256 spin_unlock_irqrestore(&ohci->event_lock, flags);
2258 spin_lock_irqsave(&ohci->event_lock, flags);
2275 spin_unlock_irqrestore(&ohci->event_lock, flags);
2280 hpsb_bus_reset(ohci->host);
2285 struct dma_trm_ctx *d = &ohci->at_req_context;
2287 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2288 if (reg_read(ohci, d->ctrlSet) & 0x800)
2289 ohci1394_stop_context(ohci, d->ctrlClear,
2297 struct dma_trm_ctx *d = &ohci->at_resp_context;
2299 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2300 if (reg_read(ohci, d->ctrlSet) & 0x800)
2301 ohci1394_stop_context(ohci, d->ctrlClear,
2308 struct dma_rcv_ctx *d = &ohci->ar_req_context;
2310 reg_read(ohci, d->ctrlSet));
2311 if (reg_read(ohci, d->ctrlSet) & 0x800)
2312 ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
2318 struct dma_rcv_ctx *d = &ohci->ar_resp_context;
2320 reg_read(ohci, d->ctrlSet));
2321 if (reg_read(ohci, d->ctrlSet) & 0x800)
2322 ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
2330 rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
2331 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event);
2332 ohci_schedule_iso_tasklets(ohci, rx_event, 0);
2338 tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
2339 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event);
2340 ohci_schedule_iso_tasklets(ohci, 0, tx_event);
2345 node_id = reg_read(ohci, OHCI1394_NodeID);
2362 handle_selfid(ohci, host, phyid, isroot);
2366 spin_lock_irqsave(&ohci->event_lock, flags);
2367 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2368 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2369 spin_unlock_irqrestore(&ohci->event_lock, flags);
2376 reg_write(ohci, OHCI1394_PhyReqFilterHiSet,
2378 reg_write(ohci, OHCI1394_PhyReqFilterLoSet,
2383 reg_read(ohci, OHCI1394_PhyReqFilterHiSet),
2384 reg_read(ohci, OHCI1394_PhyReqFilterLoSet));
2407 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2420 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
2427 reg_write(ohci, d->ctrlSet, 0x1000);
2472 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2491 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf;
2494 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming);
2498 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming),
2500 ohci1394_stop_context(ohci, d->ctrlClear, msg);
2511 ohci1394_stop_context(ohci, d->ctrlClear,
2572 if (!ohci->no_swap_incoming)
2578 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f,
2579 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3,
2583 ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f)
2586 hpsb_packet_received(ohci->host, d->spb,
2611 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2717 hpsb_packet_sent(ohci->host, packet, ack);
2720 pci_unmap_single(ohci->dev,
2728 dma_trm_flush(ohci, d);
2736 struct ti_ohci *ohci = d->ohci;
2738 if (ohci == NULL)
2747 ohci->dev, d->buf_size,
2764 d->ohci = NULL;
2768 alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
2776 d->ohci = ohci;
2816 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2827 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
2865 struct ti_ohci *ohci = d->ohci;
2867 if (ohci == NULL)
2883 d->ohci = NULL;
2887 alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
2895 d->ohci = ohci;
2914 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2948 struct ti_ohci *ohci = host->hostdata;
2950 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0]));
2951 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2]));
2953 memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN);
2960 struct ti_ohci *ohci = host->hostdata;
2963 reg_write(ohci, OHCI1394_CSRData, data);
2964 reg_write(ohci, OHCI1394_CSRCompareData, compare);
2965 reg_write(ohci, OHCI1394_CSRControl, reg & 0x3);
2968 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
2974 return reg_read(ohci, OHCI1394_CSRData);
3024 struct ti_ohci *ohci; /* shortcut to currently handled device */
3041 ohci = host->hostdata;
3042 ohci->dev = dev;
3043 ohci->host = host;
3044 ohci->init_state = OHCI_INIT_ALLOC_HOST;
3046 pci_set_drvdata(dev, ohci);
3056 ohci->no_swap_incoming = 1;
3057 ohci->selfid_swap = 0;
3059 ohci->selfid_swap = 1;
3073 ohci->check_busreset = 1;
3076 * fail to report the right length. Anyway, the ohci spec
3090 ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;
3092 ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE);
3093 if (ohci->registers == NULL) {
3098 ohci->init_state = OHCI_INIT_HAVE_IOMAPPING;
3099 DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers);
3102 ohci->csr_config_rom_cpu =
3103 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3104 &ohci->csr_config_rom_bus);
3105 if (ohci->csr_config_rom_cpu == NULL) {
3109 ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER;
3112 ohci->selfid_buf_cpu =
3113 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3114 &ohci->selfid_buf_bus);
3115 if (ohci->selfid_buf_cpu == NULL) {
3119 ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER;
3121 if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
3124 ohci->selfid_buf_cpu);
3127 ohci->self_id_errors = 0;
3129 ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE;
3131 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context,
3139 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context,
3147 if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context,
3154 if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context,
3162 ohci_soft_reset(ohci);
3168 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3171 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3172 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3175 reg_read(ohci, OHCI1394_Version);
3179 ohci->nb_iso_rcv_ctx =
3180 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
3181 ohci->nb_iso_xmit_ctx =
3182 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
3186 ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx;
3187 ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx;
3189 INIT_LIST_HEAD(&ohci->iso_tasklet_list);
3190 spin_lock_init(&ohci->iso_tasklet_list_lock);
3191 ohci->ISO_channel_usage = 0;
3192 spin_lock_init(&ohci->IR_channel_lock);
3194 spin_lock_init(&ohci->event_lock);
3203 OHCI1394_DRIVER_NAME, ohci);
3208 ohci->init_state = OHCI_INIT_HAVE_IRQ;
3209 ohci_initialize(ohci);
3212 host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi);
3213 host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo);
3215 host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;
3216 host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;
3220 (u64) reg_read(ohci, OHCI1394_PhyUpperBound) << 16;
3231 ohci->init_state = OHCI_INIT_DONE;
3241 struct ti_ohci *ohci;
3244 ohci = pci_get_drvdata(dev);
3245 if (!ohci)
3248 device = get_device(&ohci->host->device);
3250 switch (ohci->init_state) {
3252 hpsb_remove_host(ohci->host);
3255 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3256 reg_write(ohci, OHCI1394_BusOptions,
3257 (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3259 memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN);
3263 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3264 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3265 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3266 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3267 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3268 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3271 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3274 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3277 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3281 ohci_soft_reset(ohci);
3282 free_irq(dev->irq, ohci);
3287 free_dma_rcv_ctx(&ohci->ar_req_context);
3288 free_dma_rcv_ctx(&ohci->ar_resp_context);
3289 free_dma_trm_ctx(&ohci->at_req_context);
3290 free_dma_trm_ctx(&ohci->at_resp_context);
3294 ohci->selfid_buf_cpu,
3295 ohci->selfid_buf_bus);
3299 ohci->csr_config_rom_cpu,
3300 ohci->csr_config_rom_bus);
3303 iounmap(ohci->registers);
3323 struct ti_ohci *ohci = pci_get_drvdata(dev);
3325 if (!ohci) {
3333 hpsb_bus_reset(ohci->host);
3336 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3337 reg_write(ohci, OHCI1394_BusOptions,
3338 (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3340 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3341 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3342 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3343 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3344 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3345 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3346 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3347 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3348 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3349 ohci_soft_reset(ohci);
3351 free_irq(dev->irq, ohci);
3368 struct ti_ohci *ohci = pci_get_drvdata(dev);
3370 if (!ohci) {
3387 ohci_soft_reset(ohci);
3388 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3389 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3390 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3391 reg_read(ohci, OHCI1394_Version);
3395 OHCI1394_DRIVER_NAME, ohci);
3401 ohci_initialize(ohci);
3403 hpsb_resume_host(ohci->host);
3438 module to hook into ohci's interrupt handler */
3441 int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
3446 reg_write(ohci, reg, 0x8000);
3449 while (reg_read(ohci, reg) & 0x400) {
3474 int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
3481 n = ohci->nb_iso_xmit_ctx;
3482 usage = &ohci->it_ctx_usage;
3485 n = ohci->nb_iso_rcv_ctx;
3486 usage = &ohci->ir_ctx_usage;
3490 if (test_and_set_bit(0, &ohci->ir_multichannel_used)) {
3496 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3501 list_add_tail(&tasklet->link, &ohci->iso_tasklet_list);
3506 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3511 void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
3518 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3521 clear_bit(tasklet->context, &ohci->it_ctx_usage);
3523 clear_bit(tasklet->context, &ohci->ir_ctx_usage);
3526 clear_bit(0, &ohci->ir_multichannel_used);
3532 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);