Lines Matching refs:x1
48 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
50 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
52 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
53 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
54 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
55 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
56 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
57 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
58 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
63 #define I2C_MCR_OP (0x1 << 0) /* Operation */
66 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
68 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
79 #define I2C_IT_TXFE (0x1 << 0)
80 #define I2C_IT_TXFNE (0x1 << 1)
81 #define I2C_IT_TXFF (0x1 << 2)
82 #define I2C_IT_TXFOVR (0x1 << 3)
83 #define I2C_IT_RXFE (0x1 << 4)
84 #define I2C_IT_RXFNF (0x1 << 5)
85 #define I2C_IT_RXFF (0x1 << 6)
86 #define I2C_IT_RFSR (0x1 << 16)
87 #define I2C_IT_RFSE (0x1 << 17)
88 #define I2C_IT_WTSR (0x1 << 18)
89 #define I2C_IT_MTD (0x1 << 19)
90 #define I2C_IT_STD (0x1 << 20)
91 #define I2C_IT_MAL (0x1 << 24)
92 #define I2C_IT_BERR (0x1 << 25)
93 #define I2C_IT_MTDWS (0x1 << 28)
538 * wr_buff[0] = 0x1;