Lines Matching defs:ohci
53 #include "ohci.h"
90 struct fw_ohci *ohci;
117 struct fw_ohci *ohci;
486 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
488 writel(data, ohci->registers + offset);
491 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
493 return readl(ohci->registers + offset);
496 static inline void flush_writes(const struct fw_ohci *ohci)
499 reg_read(ohci, OHCI1394_Version);
502 static int read_phy_reg(struct fw_ohci *ohci, int addr)
507 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
509 val = reg_read(ohci, OHCI1394_PhyControl);
525 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
529 reg_write(ohci, OHCI1394_PhyControl,
532 val = reg_read(ohci, OHCI1394_PhyControl);
544 static int update_phy_reg(struct fw_ohci *ohci, int addr,
547 int ret = read_phy_reg(ohci, addr);
558 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
561 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
565 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
569 return read_phy_reg(ohci, addr);
574 struct fw_ohci *ohci = fw_ohci(card);
577 mutex_lock(&ohci->phy_reg_mutex);
578 ret = read_phy_reg(ohci, addr);
579 mutex_unlock(&ohci->phy_reg_mutex);
587 struct fw_ohci *ohci = fw_ohci(card);
590 mutex_lock(&ohci->phy_reg_mutex);
591 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
592 mutex_unlock(&ohci->phy_reg_mutex);
599 struct device *dev = ctx->ohci->card.device;
624 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
625 flush_writes(ctx->ohci);
640 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
647 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
654 struct fw_ohci *ohci = ctx->ohci;
708 p.generation = ohci->request_generation;
734 if (!(ohci->quirks & QUIRK_RESET_PACKET))
735 ohci->request_generation = (p.header[2] >> 16) & 0xff;
736 } else if (ctx == &ohci->ar_request_ctx) {
737 fw_core_handle_request(&ohci->card, &p);
739 fw_core_handle_response(&ohci->card, &p);
748 struct fw_ohci *ohci = ctx->ohci;
817 dma_free_coherent(ohci->card.device, PAGE_SIZE,
834 struct fw_ohci *ohci, u32 regs)
839 ctx->ohci = ohci;
860 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
861 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
862 flush_writes(ctx->ohci);
913 spin_lock_irqsave(&ctx->ohci->lock, flags);
915 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
923 * context. Must be called with ohci->lock held.
938 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
954 static int context_init(struct context *ctx, struct fw_ohci *ohci,
957 ctx->ohci = ohci;
988 struct fw_card *card = &ctx->ohci->card;
997 /* Must be called with ohci->lock held */
1031 struct fw_ohci *ohci = ctx->ohci;
1033 reg_write(ohci, COMMAND_PTR(ctx->regs),
1035 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1036 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1037 flush_writes(ohci);
1054 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1055 flush_writes(ctx->ohci);
1063 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1064 flush_writes(ctx->ohci);
1067 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1088 struct fw_ohci *ohci = ctx->ohci;
1161 dma_map_single(ohci->card.device, packet->payload,
1163 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1183 if (ohci->generation != packet->generation ||
1184 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1186 dma_unmap_single(ohci->card.device, payload_bus,
1195 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1208 struct fw_ohci *ohci = context->ohci;
1222 dma_unmap_single(ohci->card.device, packet->payload_bus,
1267 packet->callback(packet, &ohci->card, packet->ack);
1278 static void handle_local_rom(struct fw_ohci *ohci,
1299 (void *) ohci->config_rom + i, length);
1302 fw_core_handle_response(&ohci->card, &response);
1305 static void handle_local_lock(struct fw_ohci *ohci,
1332 reg_write(ohci, OHCI1394_CSRData, lock_data);
1333 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1334 reg_write(ohci, OHCI1394_CSRControl, sel);
1337 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1338 lock_old = cpu_to_be32(reg_read(ohci,
1350 fw_core_handle_response(&ohci->card, &response);
1357 if (ctx == &ctx->ohci->at_request_ctx) {
1359 packet->callback(packet, &ctx->ohci->card, packet->ack);
1370 handle_local_rom(ctx->ohci, packet, csr);
1376 handle_local_lock(ctx->ohci, packet, csr);
1379 if (ctx == &ctx->ohci->at_request_ctx)
1380 fw_core_handle_request(&ctx->ohci->card, packet);
1382 fw_core_handle_response(&ctx->ohci->card, packet);
1386 if (ctx == &ctx->ohci->at_response_ctx) {
1388 packet->callback(packet, &ctx->ohci->card, packet->ack);
1397 spin_lock_irqsave(&ctx->ohci->lock, flags);
1399 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1400 ctx->ohci->generation == packet->generation) {
1401 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1407 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1410 packet->callback(packet, &ctx->ohci->card, packet->ack);
1440 static u32 get_cycle_time(struct fw_ohci *ohci)
1447 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1449 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1452 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1456 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1476 static u32 update_bus_time(struct fw_ohci *ohci)
1478 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1480 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1481 ohci->bus_time += 0x40;
1483 return ohci->bus_time | cycle_time_seconds;
1488 struct fw_ohci *ohci = (struct fw_ohci *)data;
1496 reg = reg_read(ohci, OHCI1394_NodeID);
1505 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1509 if (!(ohci->is_root && is_new_root))
1510 reg_write(ohci, OHCI1394_LinkControlSet,
1512 ohci->is_root = is_new_root;
1514 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1530 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1534 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1538 ohci->self_id_buffer[j] =
1539 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1557 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1564 spin_lock_irqsave(&ohci->lock, flags);
1566 ohci->generation = generation;
1567 context_stop(&ohci->at_request_ctx);
1568 context_stop(&ohci->at_response_ctx);
1569 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1571 if (ohci->quirks & QUIRK_RESET_PACKET)
1572 ohci->request_generation = generation;
1583 if (ohci->next_config_rom != NULL) {
1584 if (ohci->next_config_rom != ohci->config_rom) {
1585 free_rom = ohci->config_rom;
1586 free_rom_bus = ohci->config_rom_bus;
1588 ohci->config_rom = ohci->next_config_rom;
1589 ohci->config_rom_bus = ohci->next_config_rom_bus;
1590 ohci->next_config_rom = NULL;
1598 reg_write(ohci, OHCI1394_BusOptions,
1599 be32_to_cpu(ohci->config_rom[2]));
1600 ohci->config_rom[0] = ohci->next_header;
1601 reg_write(ohci, OHCI1394_ConfigROMhdr,
1602 be32_to_cpu(ohci->next_header));
1606 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1607 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1610 spin_unlock_irqrestore(&ohci->lock, flags);
1613 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1616 log_selfids(ohci->node_id, generation,
1617 self_id_count, ohci->self_id_buffer);
1619 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1620 self_id_count, ohci->self_id_buffer,
1621 ohci->csr_state_setclear_abdicate);
1622 ohci->csr_state_setclear_abdicate = false;
1627 struct fw_ohci *ohci = data;
1631 event = reg_read(ohci, OHCI1394_IntEventClear);
1637 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1641 tasklet_schedule(&ohci->bus_reset_tasklet);
1644 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1647 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1650 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1653 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1655 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1656 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1660 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1664 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1665 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1669 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1683 reg_write(ohci, OHCI1394_LinkControlSet,
1693 spin_lock(&ohci->lock);
1694 update_bus_time(ohci);
1695 spin_unlock(&ohci->lock);
1701 static int software_reset(struct fw_ohci *ohci)
1705 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1708 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1726 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1732 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1738 ret = read_phy_reg(ohci, 2);
1742 ret = read_paged_phy_reg(ohci, 1, 8);
1749 if (ohci->quirks & QUIRK_NO_1394A)
1760 ret = update_phy_reg(ohci, 5, clear, set);
1768 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1771 reg_write(ohci, OHCI1394_HCControlClear,
1780 struct fw_ohci *ohci = fw_ohci(card);
1785 if (software_reset(ohci)) {
1786 fw_error("Failed to reset ohci card.\n");
1798 reg_write(ohci, OHCI1394_HCControlSet,
1801 flush_writes(ohci);
1805 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1814 reg_write(ohci, OHCI1394_HCControlClear,
1817 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1818 reg_write(ohci, OHCI1394_LinkControlSet,
1824 reg_write(ohci, OHCI1394_ATRetries,
1831 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1832 ohci->bus_time = seconds & ~0x3f;
1834 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1836 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1842 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1843 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1844 reg_write(ohci, OHCI1394_FairnessControl, 0);
1845 card->priority_budget_implemented = ohci->pri_req_max != 0;
1847 ar_context_run(&ohci->ar_request_ctx);
1848 ar_context_run(&ohci->ar_response_ctx);
1850 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1851 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1852 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1854 ret = configure_1394a_enhancements(ohci);
1865 ohci->next_config_rom =
1866 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1867 &ohci->next_config_rom_bus,
1869 if (ohci->next_config_rom == NULL)
1872 copy_config_rom(ohci->next_config_rom, config_rom, length);
1878 ohci->next_config_rom = ohci->config_rom;
1879 ohci->next_config_rom_bus = ohci->config_rom_bus;
1882 ohci->next_header = ohci->next_config_rom[0];
1883 ohci->next_config_rom[0] = 0;
1884 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1885 reg_write(ohci, OHCI1394_BusOptions,
1886 be32_to_cpu(ohci->next_config_rom[2]));
1887 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1889 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1891 if (!(ohci->quirks & QUIRK_NO_MSI))
1895 ohci_driver_name, ohci)) {
1898 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1899 ohci->config_rom, ohci->config_rom_bus);
1914 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1916 reg_write(ohci, OHCI1394_HCControlSet,
1919 flush_writes(ohci);
1922 fw_schedule_bus_reset(&ohci->card, false, true);
1930 struct fw_ohci *ohci;
1936 ohci = fw_ohci(card);
1940 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1945 spin_lock_irqsave(&ohci->lock, flags);
1947 if (ohci->next_config_rom == NULL) {
1948 ohci->next_config_rom = next_config_rom;
1949 ohci->next_config_rom_bus = next_config_rom_bus;
1951 copy_config_rom(ohci->next_config_rom, config_rom, length);
1953 ohci->next_header = config_rom[0];
1954 ohci->next_config_rom[0] = 0;
1956 reg_write(ohci, OHCI1394_ConfigROMmap,
1957 ohci->next_config_rom_bus);
1961 spin_unlock_irqrestore(&ohci->lock, flags);
1971 fw_schedule_bus_reset(&ohci->card, true, true);
1973 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1981 struct fw_ohci *ohci = fw_ohci(card);
1983 at_context_transmit(&ohci->at_request_ctx, packet);
1988 struct fw_ohci *ohci = fw_ohci(card);
1990 at_context_transmit(&ohci->at_response_ctx, packet);
1995 struct fw_ohci *ohci = fw_ohci(card);
1996 struct context *ctx = &ohci->at_request_ctx;
2006 dma_unmap_single(ohci->card.device, packet->payload_bus,
2012 packet->callback(packet, &ohci->card, packet->ack);
2026 struct fw_ohci *ohci = fw_ohci(card);
2031 spin_lock_irqsave(&ohci->lock, flags);
2033 if (ohci->generation != generation) {
2045 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2047 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2049 flush_writes(ohci);
2051 spin_unlock_irqrestore(&ohci->lock, flags);
2059 struct fw_ohci *ohci = fw_ohci(card);
2066 if (ohci->is_root &&
2067 (reg_read(ohci, OHCI1394_LinkControlSet) &
2072 if (ohci->csr_state_setclear_abdicate)
2078 return reg_read(ohci, OHCI1394_NodeID) << 16;
2081 return get_cycle_time(ohci);
2089 spin_lock_irqsave(&ohci->lock, flags);
2090 value = update_bus_time(ohci);
2091 spin_unlock_irqrestore(&ohci->lock, flags);
2095 value = reg_read(ohci, OHCI1394_ATRetries);
2099 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2100 (ohci->pri_req_max << 8);
2110 struct fw_ohci *ohci = fw_ohci(card);
2115 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2116 reg_write(ohci, OHCI1394_LinkControlClear,
2118 flush_writes(ohci);
2121 ohci->csr_state_setclear_abdicate = false;
2125 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2126 reg_write(ohci, OHCI1394_LinkControlSet,
2128 flush_writes(ohci);
2131 ohci->csr_state_setclear_abdicate = true;
2135 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2136 flush_writes(ohci);
2140 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2141 reg_write(ohci, OHCI1394_IntEventSet,
2143 flush_writes(ohci);
2147 spin_lock_irqsave(&ohci->lock, flags);
2148 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2149 spin_unlock_irqrestore(&ohci->lock, flags);
2155 reg_write(ohci, OHCI1394_ATRetries, value);
2156 flush_writes(ohci);
2160 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2161 flush_writes(ohci);
2279 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2283 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2284 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2285 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2286 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2288 ohci->mc_channels = channels;
2294 struct fw_ohci *ohci = fw_ohci(card);
2302 spin_lock_irqsave(&ohci->lock, flags);
2306 mask = &ohci->it_context_mask;
2312 ctx = &ohci->it_context_list[index];
2317 channels = &ohci->ir_context_channels;
2318 mask = &ohci->ir_context_mask;
2325 ctx = &ohci->ir_context_list[index];
2330 mask = &ohci->ir_context_mask;
2332 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2334 ohci->mc_allocated = true;
2337 ctx = &ohci->ir_context_list[index];
2346 spin_unlock_irqrestore(&ohci->lock, flags);
2358 ret = context_init(&ctx->context, ohci, regs, callback);
2363 set_multichannel_mask(ohci, 0);
2370 spin_lock_irqsave(&ohci->lock, flags);
2378 ohci->mc_allocated = false;
2383 spin_unlock_irqrestore(&ohci->lock, flags);
2392 struct fw_ohci *ohci = ctx->context.ohci;
2398 index = ctx - ohci->it_context_list;
2404 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2405 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2413 index = ctx - ohci->ir_context_list;
2420 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2421 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2422 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2432 struct fw_ohci *ohci = fw_ohci(base->card);
2438 index = ctx - ohci->it_context_list;
2439 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2444 index = ctx - ohci->ir_context_list;
2445 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2448 flush_writes(ohci);
2456 struct fw_ohci *ohci = fw_ohci(base->card);
2465 spin_lock_irqsave(&ohci->lock, flags);
2469 index = ctx - ohci->it_context_list;
2470 ohci->it_context_mask |= 1 << index;
2474 index = ctx - ohci->ir_context_list;
2475 ohci->ir_context_mask |= 1 << index;
2476 ohci->ir_context_channels |= 1ULL << base->channel;
2480 index = ctx - ohci->ir_context_list;
2481 ohci->ir_context_mask |= 1 << index;
2482 ohci->ir_context_channels |= ohci->mc_channels;
2483 ohci->mc_channels = 0;
2484 ohci->mc_allocated = false;
2488 spin_unlock_irqrestore(&ohci->lock, flags);
2493 struct fw_ohci *ohci = fw_ohci(base->card);
2500 spin_lock_irqsave(&ohci->lock, flags);
2503 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2504 *channels = ohci->ir_context_channels;
2507 set_multichannel_mask(ohci, *channels);
2511 spin_unlock_irqrestore(&ohci->lock, flags);
2751 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2763 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2820 struct fw_ohci *ohci;
2826 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2827 if (ohci == NULL) {
2832 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2844 pci_set_drvdata(dev, ohci);
2846 spin_lock_init(&ohci->lock);
2847 mutex_init(&ohci->phy_reg_mutex);
2849 tasklet_init(&ohci->bus_reset_tasklet,
2850 bus_reset_tasklet, (unsigned long)ohci);
2858 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2859 if (ohci->registers == NULL) {
2871 ohci->quirks = ohci_quirks[i].flags;
2875 ohci->quirks = param_quirks;
2877 ar_context_init(&ohci->ar_request_ctx, ohci,
2880 ar_context_init(&ohci->ar_response_ctx, ohci,
2883 context_init(&ohci->at_request_ctx, ohci,
2886 context_init(&ohci->at_response_ctx, ohci,
2889 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2890 ohci->ir_context_channels = ~0ULL;
2891 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2892 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2893 n_ir = hweight32(ohci->ir_context_mask);
2895 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2897 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2898 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2899 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2900 n_it = hweight32(ohci->it_context_mask);
2902 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2904 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2910 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2912 &ohci->self_id_bus,
2914 if (ohci->self_id_cpu == NULL) {
2919 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2922 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2923 reg_read(ohci, OHCI1394_GUIDLo);
2925 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2929 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2930 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2933 n_ir, n_it, ohci->quirks);
2938 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2939 ohci->self_id_cpu, ohci->self_id_bus);
2941 kfree(ohci->ir_context_list);
2942 kfree(ohci->it_context_list);
2943 context_release(&ohci->at_response_ctx);
2944 context_release(&ohci->at_request_ctx);
2945 ar_context_release(&ohci->ar_response_ctx);
2946 ar_context_release(&ohci->ar_request_ctx);
2947 pci_iounmap(dev, ohci->registers);
2953 kfree(&ohci->card);
2964 struct fw_ohci *ohci;
2966 ohci = pci_get_drvdata(dev);
2967 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2968 flush_writes(ohci);
2969 fw_core_remove_card(&ohci->card);
2972 software_reset(ohci);
2973 free_irq(dev->irq, ohci);
2975 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2976 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2977 ohci->next_config_rom, ohci->next_config_rom_bus);
2978 if (ohci->config_rom)
2979 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2980 ohci->config_rom, ohci->config_rom_bus);
2981 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2982 ohci->self_id_cpu, ohci->self_id_bus);
2983 ar_context_release(&ohci->ar_request_ctx);
2984 ar_context_release(&ohci->ar_response_ctx);
2985 context_release(&ohci->at_request_ctx);
2986 context_release(&ohci->at_response_ctx);
2987 kfree(ohci->it_context_list);
2988 kfree(ohci->ir_context_list);
2990 pci_iounmap(dev, ohci->registers);
2993 kfree(&ohci->card);
2996 fw_notify("Removed fw-ohci device.\n");
3002 struct fw_ohci *ohci = pci_get_drvdata(dev);
3005 software_reset(ohci);
3006 free_irq(dev->irq, ohci);
3023 struct fw_ohci *ohci = pci_get_drvdata(dev);
3035 return ohci_enable(&ohci->card, NULL, 0);