Lines Matching refs:amd_irongate_private
34 } amd_irongate_private;
86 tables = amd_irongate_private.gatt_pages;
87 for (i = 0; i < amd_irongate_private.num_tables; i++) {
96 amd_irongate_private.gatt_pages = NULL;
121 amd_irongate_private.num_tables = i;
122 amd_irongate_private.gatt_pages = tables;
138 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
177 writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
234 if (!amd_irongate_private.registers) {
238 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
239 if (!amd_irongate_private.registers)
244 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
245 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
254 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
256 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
257 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
265 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
266 readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
278 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
280 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
281 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
287 iounmap((void __iomem *) amd_irongate_private.registers);
300 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
301 readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
445 bridge->dev_private_data = &amd_irongate_private,