Lines Matching refs:dmac
2 * include/asm-xtensa/variant-s6000/dmac.h
75 #define DMA_CHNL(dmac, n) ((dmac) + 0x1000 + (n) * 0x100)
132 #define S6_DMAC_INDEX(dmac) (((unsigned)(dmac) >> 18) % S6_DMAC_NB)
135 u32 dmac;
145 static inline int s6dmac_fifo_full(u32 dmac, int chan)
147 return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
151 static inline int s6dmac_termcnt_irq(u32 dmac, int chan)
154 int r = (readl(dmac + S6_DMA_TERMCNTIRQSTAT) & m) && 1;
156 writel(m, dmac + S6_DMA_TERMCNTIRQCLR);
160 static inline int s6dmac_pendcnt_irq(u32 dmac, int chan)
163 int r = (readl(dmac + S6_DMA_PENDCNTIRQSTAT) & m) && 1;
165 writel(m, dmac + S6_DMA_PENDCNTIRQCLR);
169 static inline int s6dmac_lowwmark_irq(u32 dmac, int chan)
171 int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0;
173 writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR);
177 static inline u32 s6dmac_pending_count(u32 dmac, int chan)
179 return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
184 static inline void s6dmac_set_terminal_count(u32 dmac, int chan, u32 n)
187 n |= readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB)
189 writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
192 static inline u32 s6dmac_get_terminal_count(u32 dmac, int chan)
194 return (readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB))
198 static inline u32 s6dmac_timestamp(u32 dmac, int chan)
200 return readl(DMA_CHNL(dmac, chan) + S6_DMA_TIMESTAMP);
203 static inline u32 s6dmac_cur_src(u32 dmac, int chan)
205 return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_SRC);
208 static inline u32 s6dmac_cur_dst(u32 dmac, int chan)
210 return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_DST);
213 static inline void s6dmac_disable_chan(u32 dmac, int chan)
216 writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
218 DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
220 ctrl = readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
224 static inline void s6dmac_set_stride_skip(u32 dmac, int chan,
228 writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
229 writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
230 writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
233 static inline void s6dmac_enable_chan(u32 dmac, int chan,
245 writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
246 writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO);
248 DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
249 s6dmac_set_stride_skip(dmac, chan, comchunk, srcskip, dstskip);
261 DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
267 static inline unsigned _dmac_addr_index(u32 dmac)
269 unsigned i = S6_DMAC_INDEX(dmac);
270 if (s6dmac_ctrl[i].dmac != dmac)
275 static inline void _s6dmac_disable_error_irqs(u32 dmac, u32 mask)
277 writel(mask, dmac + S6_DMA_TERMCNTIRQCLR);
278 writel(mask, dmac + S6_DMA_PENDCNTIRQCLR);
279 writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR);
280 writel(readl(dmac + S6_DMA_INTENABLE0)
282 dmac + S6_DMA_INTENABLE0);
283 writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL),
284 dmac + S6_DMA_INTENABLE1);
286 dmac + S6_DMA_INTCLEAR0);
287 writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1);
296 static inline int s6dmac_request_chan(u32 dmac, int chan,
310 spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
313 r = (readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_CHAN)
316 if (r >= s6dmac_ctrl[_dmac_addr_index(dmac)].chan_nb) {
321 } else if (((readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_ENA)
325 s6dmac_enable_chan(dmac, r, prio, periphxfer,
333 static inline void s6dmac_put_fifo(u32 dmac, int chan,
337 spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
339 writel(src, dmac + S6_DMA_DESCRFIFO0);
340 writel(dst, dmac + S6_DMA_DESCRFIFO1);
341 writel(size, dmac + S6_DMA_DESCRFIFO2);
342 writel(chan, dmac + S6_DMA_DESCRFIFO3);
346 static inline u32 s6dmac_channel_enabled(u32 dmac, int chan)
348 return readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) &
357 static inline void s6dmac_dp_setup_group(u32 dmac, int port,
361 BUG_ON(dmac != S6_REG_DPDMA);
366 dmac + S6_DMA_DPORTCTRLGRP(port));
369 static inline void s6dmac_dp_switch_group(u32 dmac, int port, int enable)
372 BUG_ON(dmac != S6_REG_DPDMA);
373 tmp = readl(dmac + S6_DMA_DPORTCTRLGRP(port));
378 writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port));
381 extern void s6dmac_put_fifo_cache(u32 dmac, int chan,
383 extern void s6dmac_disable_error_irqs(u32 dmac, u32 mask);
384 extern u32 s6dmac_int_sources(u32 dmac, u32 channel);
385 extern void s6dmac_release_chan(u32 dmac, int chan);