Lines Matching defs:IO_STATE
325 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
326 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
327 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
328 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
329 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
333 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
368 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) |
369 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
370 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) |
371 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
372 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) |
373 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) |
374 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) |
375 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) |
376 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) |
377 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) |
378 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) |
379 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) |
380 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) |
381 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) |
382 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) |
383 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) |
384 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
385 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
386 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) |
387 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
388 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
389 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
392 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
395 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
505 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop,
507 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr,
510 IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop,
512 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr,
515 IO_STATE(R_IRQ_MASK2_SET, dma8_eop,
517 IO_STATE(R_IRQ_MASK2_SET, dma9_descr,
560 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop,
562 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr,
565 IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop,
567 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr,
570 IO_STATE(R_IRQ_MASK2_SET, dma4_eop,
572 IO_STATE(R_IRQ_MASK2_SET, dma5_descr,
705 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
706 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
716 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
717 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
1205 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1238 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1263 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
1264 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
1347 *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD,
1350 *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR,
1376 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1380 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1388 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1393 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1397 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):