Lines Matching refs:Fld
101 #define SMCR_DCAC Fld(2,0) /* Number of column address bits */
102 #define SMCR_DRAC Fld(2,2) /* Number of row address bits */
104 #define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */
111 #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */
112 #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */
114 #define SNPR_BankSelect Fld(2,27) /* Bank select */
145 #define VMCCR_RefPeriod Fld(2,3) /* Refresh period */
146 #define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */
149 #define VMCCR_RefLow Fld(6,11) /* refresh low counter */
150 #define VMCCR_RefHigh Fld(7,17) /* refresh high counter */
151 #define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */
179 #define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */
213 #define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */
214 #define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */
217 #define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */
218 #define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */
219 #define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */
223 #define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */
225 #define DACDR_DACCount Fld(8,0) /* Count value */
300 #define IEEE_Config_M Fld(3,0) /* Mode select */
311 #define IEEE_Data_Db Fld(9,16) /* Data byte 2 */
312 #define IEEE_Data_Da Fld(9,0) /* Data byte 1 */
313 #define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */
335 #define IEEE_InitTime_TimValInit Fld(22,0)
336 #define IEEE_TimerStatus_TimValStat Fld(22,0)
337 #define IEEE_ReloadValue_Reload Fld(4,0)
340 #define IEEE_TestControl_ClockSelect Fld(2,1)
402 #define VideoControl_VCompVal Fld(2,2)
403 #define VideoControl_VgaReq Fld(4,4)
404 #define VideoControl_VBurstL Fld(4,8)
408 #define VgaTiming0_PPL Fld(6,2)
409 #define VgaTiming0_HSW Fld(8,8)
410 #define VgaTiming0_HFP Fld(8,16)
411 #define VgaTiming0_HBP Fld(8,24)
413 #define VgaTiming1_LPS Fld(10,0)
414 #define VgaTiming1_VSW Fld(6,10)
415 #define VgaTiming1_VFP Fld(8,16)
416 #define VgaTiming1_VBP Fld(8,24)
423 #define VgaTiming3_HBS Fld(8,0)
424 #define VgaTiming3_HBE Fld(8,8)
425 #define VgaTiming3_VBS Fld(8,16)
426 #define VgaTiming3_VBE Fld(8,24)
428 #define VgaBorder_BCOL Fld(24,0)
438 #define VgaPalette_R Fld(8,0)
439 #define VgaPalette_G Fld(8,8)
440 #define VgaPalette_B Fld(8,16)
445 #define DacControl_RTrim Fld(5,4)
446 #define DacControl_GTrim Fld(5,9)
447 #define DacControl_BTrim Fld(5,14)
450 #define VgaTest_Datatest Fld(4,1)
452 #define VgaTest_DACTESTOUT Fld(3,5)
566 #define USTCR_RdBstCntrl Fld(3,0)
567 #define USTCR_ByteEnable Fld(4,3)
713 #define KBDCLKDIV_DivVal Fld(4,0)
728 #define MSECLKDIV_DivVal Fld(4,0)
733 #define KBDTEST1_C Fld(2,3)
761 #define MSETEST1_C Fld(2,3)