Lines Matching refs:__REG
8 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
12 #define UDCCR __REG(0x40600000) /* UDC Control Register */
22 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
33 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
46 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
59 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
70 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
82 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
94 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95 #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96 #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102 #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103 #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104 #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
119 #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
130 #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
141 #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
152 #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */