Lines Matching refs:AT91_MC
20 #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
23 #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
43 #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
45 #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
52 #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
65 #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
69 #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
91 #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
102 #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
105 #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
127 #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
128 #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
129 #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
130 #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
131 #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
132 #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
135 #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */