Lines Matching refs:AT91_AIC
19 #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
27 #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
28 #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
29 #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
30 #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
33 #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
34 #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
35 #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
39 #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
40 #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
41 #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
42 #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
43 #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
44 #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
45 #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
49 #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
50 #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
51 #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */