Lines Matching refs:sbh
107 static char *sb_devpathvar(sb_t *sbh, char *var, int len, const char *name);
110 static void sb_war43448(sb_t *sbh);
111 static void sb_war43448_aspm(sb_t *sbh);
112 static void sb_war32414_forceHT(sb_t *sbh, bool forceHT);
114 static void sb_war42767(sb_t *sbh);
115 static void sb_war42767_clkreq(sb_t *sbh);
129 #define SB_INFO(sbh) (sb_info_t*)(uintptr)sbh
538 BCMINITFN(sb_war42780_clkreq)(sb_t *sbh, bool clkreq)
542 si = SB_INFO(sbh);
548 sb_pcieclkreq(sbh, 1, (int32)clkreq);
552 BCMINITFN(sb_war43448)(sb_t *sbh)
556 si = SB_INFO(sbh);
569 BCMINITFN(sb_war43448_aspm)(sb_t *sbh)
576 si = SB_INFO(sbh);
586 pcieregs = (sbpcieregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
606 BCMINITFN(sb_war32414_forceHT)(sb_t *sbh, bool forceHT)
611 si = SB_INFO(sbh);
618 sb_corereg(sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
623 sb_coreid(sb_t *sbh)
628 si = SB_INFO(sbh);
635 sb_flag(sb_t *sbh)
640 si = SB_INFO(sbh);
647 sb_coreidx(sb_t *sbh)
651 si = SB_INFO(sbh);
712 sb_corevendor(sb_t *sbh)
717 si = SB_INFO(sbh);
724 sb_corerev(sb_t *sbh)
730 si = SB_INFO(sbh);
738 sb_osh(sb_t *sbh)
742 si = SB_INFO(sbh);
747 sb_setosh(sb_t *sbh, osl_t *osh)
751 si = SB_INFO(sbh);
761 sb_coreflags_wo(sb_t *sbh, uint32 mask, uint32 val)
767 si = SB_INFO(sbh);
779 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
785 si = SB_INFO(sbh);
804 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
810 si = SB_INFO(sbh);
828 sb_corebist(sb_t *sbh)
835 si = SB_INFO(sbh);
852 sb_iscoreup(sb_t *sbh)
857 si = SB_INFO(sbh);
874 sb_corereg(sb_t *sbh, uint coreidx, uint regoff, uint mask, uint val)
883 si = SB_INFO(sbh);
1050 sb_pcieclkreq(sb_t *sbh, uint32 mask, uint32 val)
1056 si = SB_INFO(sbh);
1098 sb_pci_pmecap(sb_t *sbh)
1104 si = SB_INFO(sbh);
1127 sb_pci_pmeen(sb_t *sbh)
1131 si = SB_INFO(sbh);
1134 if (!sb_pci_pmecap(sbh))
1143 sb_pcieclkreq(sbh, 1, 0);
1146 sb_pcieclkreq(sbh, 1, 1);
1154 sb_pci_pmeclr(sb_t *sbh)
1160 si = SB_INFO(sbh);
1162 if (!sb_pci_pmecap(sbh))
1382 sb_detach(sb_t *sbh)
1387 si = SB_INFO(sbh);
1422 sb_findcoreidx(sb_t *sbh, uint coreid, uint coreunit)
1428 si = SB_INFO(sbh);
1448 sb_setcoreidx(sb_t *sbh, uint coreidx)
1452 si = SB_INFO(sbh);
1531 sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
1535 idx = sb_findcoreidx(sbh, coreid, coreunit);
1539 return (sb_setcoreidx(sbh, idx));
1544 BCMINITFN(sb_chip)(sb_t *sbh)
1548 si = SB_INFO(sbh);
1554 BCMINITFN(sb_chiprev)(sb_t *sbh)
1558 si = SB_INFO(sbh);
1564 BCMINITFN(sb_chipcrev)(sb_t *sbh)
1568 si = SB_INFO(sbh);
1574 BCMINITFN(sb_chippkg)(sb_t *sbh)
1578 si = SB_INFO(sbh);
1584 BCMINITFN(sb_pcirev)(sb_t *sbh)
1588 si = SB_INFO(sbh);
1593 BCMINITFN(sb_war16165)(sb_t *sbh)
1597 si = SB_INFO(sbh);
1612 BCMINITFN(sb_pcmciarev)(sb_t *sbh)
1616 si = SB_INFO(sbh);
1622 BCMINITFN(sb_boardvendor)(sb_t *sbh)
1626 si = SB_INFO(sbh);
1632 BCMINITFN(sb_boardtype)(sb_t *sbh)
1637 si = SB_INFO(sbh);
1667 /* return bus type of sbh device */
1669 sb_bus(sb_t *sbh)
1673 si = SB_INFO(sbh);
1679 sb_buscoretype(sb_t *sbh)
1683 si = SB_INFO(sbh);
1690 sb_buscorerev(sb_t *sbh)
1693 si = SB_INFO(sbh);
1700 sb_corelist(sb_t *sbh, uint coreid[])
1704 si = SB_INFO(sbh);
1712 sb_coreregs(sb_t *sbh)
1716 si = SB_INFO(sbh);
1756 sb_taclear(sb_t *sbh)
1767 si = SB_INFO(sbh);
1788 imstate = sb_corereg(sbh, si->sb.buscoreidx,
1791 sb_corereg(sbh, si->sb.buscoreidx,
1806 imerrlog = sb_corereg(sbh, si->sb.buscoreidx, SBIMERRLOG, 0, 0);
1808 imerrloga = sb_corereg(sbh, si->sb.buscoreidx, SBIMERRLOGA,
1811 sb_corereg(sbh, si->sb.buscoreidx, SBIMERRLOG, ~0, 0);
1822 origidx = sb_coreidx(sbh);
1824 corereg = sb_setcore(sbh, SB_PCMCIA, 0);
1845 sb_setcoreidx(sbh, origidx);
1863 sb_commit(sb_t *sbh)
1869 si = SB_INFO(sbh);
1878 chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
1884 sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
1893 sb_setcoreidx(sbh, origidx);
1903 sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
1909 si = SB_INFO(sbh);
1916 sb_core_disable(sbh, (bits | resetbits));
1946 sb_core_tofixup(sb_t *sbh)
1951 si = SB_INFO(sbh);
1965 if (sb_coreid(sbh) == SB_PCI) {
1974 sb_commit(sbh);
2002 sb_set_initiator_to(sb_t *sbh, uint32 to, uint idx)
2010 si = SB_INFO(sbh);
2025 idx = sb_findcoreidx(sbh, SB_PCMCIA, 0);
2028 idx = sb_findcoreidx(sbh, SB_MIPS33, 0);
2038 origidx = sb_coreidx(sbh);
2040 sb = REGS2SB(sb_setcoreidx(sbh, idx));
2046 sb_commit(sbh);
2047 sb_setcoreidx(sbh, origidx);
2053 sb_core_disable(sb_t *sbh, uint32 bits)
2060 si = SB_INFO(sbh);
2111 sb_watchdog(sb_t *sbh, uint ticks)
2115 sb_clkctl_clk(sbh, CLK_FAST);
2117 sb_clkctl_clk(sbh, CLK_DYNAMIC);
2120 if (sbh->chip == BCM4328_CHIP_ID && ticks != 0)
2121 sb_corereg(sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, min_res_mask),
2127 sb_corereg(sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
2132 sb_pcmcia_init(sb_t *sbh)
2137 si = SB_INFO(sbh);
2148 BCMINITFN(sb_pci_up)(sb_t *sbh)
2152 si = SB_INFO(sbh);
2159 sb_war32414_forceHT(sbh, 1);
2162 sb_pcieclkreq(sbh, 1, 0);
2173 BCMUNINITFN(sb_pci_sleep)(sb_t *sbh)
2177 si = SB_INFO(sbh);
2190 BCMINITFN(sb_pci_down)(sb_t *sbh)
2194 si = SB_INFO(sbh);
2201 sb_war32414_forceHT(sbh, 0);
2204 sb_pcieclkreq(sbh, 1, 1);
2207 sb_pcieclkreq(sbh, 1, 1);
2212 BCMINITFN(sb_war42767_clkreq)(sb_t *sbh)
2218 si = SB_INFO(sbh);
2224 pcieregs = (sbpcieregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
2239 BCMINITFN(sb_war42767)(sb_t *sbh)
2244 si = SB_INFO(sbh);
2262 BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
2271 si = SB_INFO(sbh);
2289 pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
2313 sb_commit(sbh);
2320 w = sb_pcie_readreg((void *)(uintptr)sbh,
2324 sb_pcie_writereg((void *)(uintptr)sbh,
2330 w = sb_pcie_readreg((void *)(uintptr)sbh,
2334 sb_pcie_writereg((void *)(uintptr)sbh,
2342 w = sb_pcie_readreg((void *)(uintptr)sbh,
2347 sb_pcie_writereg((void *)(uintptr)sbh, (void *)(uintptr)PCIE_PCIEREGS,
2350 sb_war43448(sbh);
2352 sb_war42767(sbh);
2354 sb_war43448_aspm(sbh);
2355 sb_war42767_clkreq(sbh);
2360 sb_setcoreidx(sbh, idx);
2413 sb_coreunit(sb_t *sbh)
2421 si = SB_INFO(sbh);
2427 coreid = sb_coreid(sbh);
2537 BCMINITFN(sb_clock)(sb_t *sbh)
2546 si = SB_INFO(sbh);
2552 cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
2555 if (sbh->cccaps & CC_CAP_PMU) {
2556 rate = sb_pmu_cpu_clock(sbh, si->osh);
2560 pll_type = sbh->cccaps & CC_CAP_PLL_MASK;
2577 sb_setcoreidx(sbh, idx);
2585 BCMINITFN(sb_alp_clock)(sb_t *sbh)
2589 if (sbh->cccaps & CC_CAP_PMU)
2590 clock = sb_pmu_alp_clock(sbh, sb_osh(sbh));
2597 sb_gpiosetcore(sb_t *sbh)
2601 si = SB_INFO(sbh);
2603 return (sb_setcoreidx(sbh, SB_CC_IDX));
2608 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
2613 si = SB_INFO(sbh);
2627 return (sb_corereg(sbh, SB_CC_IDX, regoff, mask, val));
2632 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
2637 si = SB_INFO(sbh);
2651 return (sb_corereg(sbh, SB_CC_IDX, regoff, mask, val));
2656 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
2661 si = SB_INFO(sbh);
2675 return (sb_corereg(sbh, SB_CC_IDX, regoff, mask, val));
2680 sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
2684 si = SB_INFO(sbh);
2715 sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
2719 si = SB_INFO(sbh);
2746 sb_gpioin(sb_t *sbh)
2751 si = SB_INFO(sbh);
2755 return (sb_corereg(sbh, SB_CC_IDX, regoff, 0, 0));
2760 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
2765 si = SB_INFO(sbh);
2776 return (sb_corereg(sbh, SB_CC_IDX, regoff, mask, val));
2781 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
2786 si = SB_INFO(sbh);
2797 return (sb_corereg(sbh, SB_CC_IDX, regoff, mask, val));
2802 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
2806 si = SB_INFO(sbh);
2811 return (sb_corereg(sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
2816 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
2819 si = SB_INFO(sbh);
2824 return (sb_corereg(sbh, SB_CC_IDX,
2829 sb_gpiopull(sb_t *sbh, bool updown, uint32 mask, uint32 val)
2834 si = SB_INFO(sbh);
2839 return (sb_corereg(sbh, SB_CC_IDX, offs, mask, val));
2843 sb_gpioevent(sb_t *sbh, uint regtype, uint32 mask, uint32 val)
2848 si = SB_INFO(sbh);
2861 return (sb_corereg(sbh, SB_CC_IDX, offs, mask, val));
2865 BCMINITFN(sb_gpio_handler_register)(sb_t *sbh, uint32 event,
2874 si = SB_INFO(sbh);
2894 BCMINITFN(sb_gpio_handler_unregister)(sb_t *sbh, void* gpioh)
2899 si = SB_INFO(sbh);
2927 sb_gpio_handler_process(sb_t *sbh)
2932 uint32 level = sb_gpioin(sbh);
2933 uint32 edge = sb_gpioevent(sbh, GPIO_REGEVT, 0, 0);
2935 si = SB_INFO(sbh);
2945 sb_gpioevent(sbh, GPIO_REGEVT, edge, edge); /* clear edge-trigger status */
2949 sb_gpio_int_enable(sb_t *sbh, bool enable)
2954 si = SB_INFO(sbh);
2959 return (sb_corereg(sbh, SB_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0)));
3057 BCMINITFN(sb_clkctl_init)(sb_t *sbh)
3063 si = SB_INFO(sbh);
3067 if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
3085 sb_setcoreidx(sbh, origidx);
3090 BCMINITFN(sb_clkctl_fast_pwrup_delay)(sb_t *sbh)
3099 si = SB_INFO(sbh);
3105 if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
3108 if (sbh->cccaps & CC_CAP_PMU) {
3109 fpdelay = sb_pmu_fast_pwrup_delay(sbh, si->osh);
3113 if (!(sbh->cccaps & CC_CAP_PWR_CTL))
3121 sb_setcoreidx(sbh, origidx);
3128 sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
3133 si = SB_INFO(sbh);
3205 sb_clkctl_clk(sb_t *sbh, uint mode)
3213 si = SB_INFO(sbh);
3227 if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
3234 cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
3287 sb_setcoreidx(sbh, origidx);
3294 sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
3299 si = SB_INFO(sbh);
3311 sb_deregister_intr_callback(sb_t *sbh)
3315 si = SB_INFO(sbh);
3321 BCMINITFN(sb_d11_devid)(sb_t *sbh)
3323 sb_info_t *si = SB_INFO(sbh);
3328 if (sbh->chip == BCM4328_CHIP_ID &&
3329 (sbh->chippkg == BCM4328USBDUAL_PKG_ID || sbh->chippkg == BCM4328SDIODUAL_PKG_ID))
3334 if ((device = (uint16)sb_getdevpathintvar(sbh, "devid")) != 0)
3346 else if (sbh->chip == BCM4712_CHIP_ID) {
3347 if (sbh->chippkg == BCM4712SMALL_PKG_ID)
3360 BCMINITFN(sb_corepciid)(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
3367 uint32 core = sb_coreid(sbh);
3374 switch (sb_corevendor(sbh)) {
3479 device = sb_d11_devid(sbh);
3585 sb_t *sbh;
3590 sbh = (sb_t *)sb;
3591 si = SB_INFO(sbh);
3594 pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
3616 sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
3622 si = SB_INFO(sbh);
3625 pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
3649 BCMINITFN(sb_devpath)(sb_t *sbh, char *path, int size)
3658 switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
3661 slen = snprintf(path, (size_t)size, "sb/%u/", sb_coreidx(sbh));
3664 ASSERT((SB_INFO(sbh))->osh);
3666 OSL_PCI_BUS((SB_INFO(sbh))->osh),
3667 OSL_PCI_SLOT((SB_INFO(sbh))->osh));
3690 BCMINITFN(sb_getdevpathvar)(sb_t *sbh, const char *name)
3694 sb_devpathvar(sbh, varname, sizeof(varname), name);
3701 BCMINITFN(sb_getdevpathintvar)(sb_t *sbh, const char *name)
3705 sb_devpathvar(sbh, varname, sizeof(varname), name);
3716 BCMINITFN(sb_devpathvar)(sb_t *sbh, char *var, int len, const char *name)
3723 if (sb_devpath(sbh, var, len) == 0) {
3812 sb_backplane64(sb_t *sbh)
3816 si = SB_INFO(sbh);
3821 sb_btcgpiowar(sb_t *sbh)
3827 si = SB_INFO(sbh);
3838 origidx = sb_coreidx(sbh);
3840 cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
3846 sb_setcoreidx(sbh, origidx);
3853 sb_deviceremoved(sb_t *sbh)
3858 si = SB_INFO(sbh);
3876 BCMINITFN(sb_socram_size)(sb_t *sbh)
3888 si = SB_INFO(sbh);
3893 origidx = sb_coreidx(sbh);
3896 if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
3900 if (!(wasup = sb_iscoreup(sbh)))
3901 sb_core_reset(sbh, 0, 0);
3902 corerev = sb_corerev(sbh);
3924 sb_core_disable(sbh, 0);
3925 sb_setcoreidx(sbh, origidx);