Lines Matching refs:start
128 unsigned long start = KSEG0;
129 unsigned long end = (start + dcache_size);
131 while (start < end) {
132 cache16_unroll32(start,Index_Writeback_Inv_D);
133 start += 0x200;
139 unsigned long start = KSEG0;
140 unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz);
143 while (start < end) {
146 cache16_unroll32(start|way,Index_Writeback_Inv_D);
147 start += 0x200;
153 unsigned long start = page;
154 unsigned long end = (start + PAGE_SIZE);
156 while (start < end) {
157 cache16_unroll32(start,Hit_Writeback_Inv_D);
158 start += 0x200;
164 unsigned long start = page;
165 unsigned long end = (start + PAGE_SIZE);
167 while (start < end) {
168 cache16_unroll32(start,Index_Writeback_Inv_D);
169 start += 0x200;
175 unsigned long start = page;
176 unsigned long end = (start + PAGE_SIZE);
179 while (start < end) {
182 cache16_unroll32(start|way,Index_Writeback_Inv_D);
183 start += 0x200;
189 unsigned long start = KSEG0;
190 unsigned long end = (start + icache_size);
192 while (start < end) {
193 cache16_unroll32(start,Index_Invalidate_I);
194 start += 0x200;
200 unsigned long start = KSEG0;
201 unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz);
204 while (start < end) {
207 cache16_unroll32(start|way,Index_Invalidate_I);
208 start += 0x200;
214 unsigned long start = page;
215 unsigned long end = (start + PAGE_SIZE);
217 while (start < end) {
218 cache16_unroll32(start,Hit_Invalidate_I);
219 start += 0x200;
225 unsigned long start = page;
226 unsigned long end = (start + PAGE_SIZE);
228 while (start < end) {
229 cache16_unroll32(start,Index_Invalidate_I);
230 start += 0x200;
236 unsigned long start = KSEG0;
239 while (start < end) {
240 cache16_unroll32(start,Index_Writeback_Inv_SD);
241 start += 0x200;
247 unsigned long start = page;
250 while (start < end) {
251 cache16_unroll32(start,Hit_Writeback_Inv_SD);
252 start += 0x200;
258 unsigned long start = page;
261 while (start < end) {
262 cache16_unroll32(start,Index_Writeback_Inv_SD);
263 start += 0x200;
295 unsigned long start = KSEG0;
296 unsigned long end = (start + dcache_size);
298 while (start < end) {
299 cache32_unroll32(start,Index_Writeback_Inv_D);
300 start += 0x400;
306 unsigned long start = KSEG0;
307 unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz);
310 while (start < end) {
313 cache32_unroll32(start|way,Index_Writeback_Inv_D);
314 start += 0x400;
332 unsigned long start = page;
333 unsigned long end = (start + PAGE_SIZE);
338 while (start < end) {
339 cache32_unroll32(start,Hit_Writeback_Inv_D);
340 start += 0x400;
346 unsigned long start = page;
347 unsigned long end = (start + PAGE_SIZE);
349 while (start < end) {
350 cache32_unroll32(start,Index_Writeback_Inv_D);
351 start += 0x400;
357 unsigned long start = page;
358 unsigned long end = (start + PAGE_SIZE);
361 while (start < end) {
364 cache32_unroll32(start|way,Index_Writeback_Inv_D);
365 start += 0x400;
371 unsigned long start = KSEG0;
372 unsigned long end = (start + icache_size);
374 while (start < end) {
375 cache32_unroll32(start,Index_Invalidate_I);
376 start += 0x400;
382 unsigned long start = KSEG0;
383 unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz);
386 while (start < end) {
389 cache32_unroll32(start|way,Index_Invalidate_I);
390 start += 0x400;
396 unsigned long start = page;
397 unsigned long end = (start + PAGE_SIZE);
399 while (start < end) {
400 cache32_unroll32(start,Hit_Invalidate_I);
401 start += 0x400;
407 unsigned long start = page;
408 unsigned long end = (start + PAGE_SIZE);
410 while (start < end) {
411 cache32_unroll32(start,Index_Invalidate_I);
412 start += 0x400;
418 unsigned long start = KSEG0;
421 while (start < end) {
422 cache32_unroll32(start,Index_Writeback_Inv_SD);
423 start += 0x400;
429 unsigned long start = page;
432 while (start < end) {
433 cache32_unroll32(start,Hit_Writeback_Inv_SD);
434 start += 0x400;
440 unsigned long start = page;
443 while (start < end) {
444 cache32_unroll32(start,Index_Writeback_Inv_SD);
445 start += 0x400;
477 unsigned long start = KSEG0;
480 while (start < end) {
481 cache64_unroll32(start,Index_Writeback_Inv_SD);
482 start += 0x800;
488 unsigned long start = page;
491 while (start < end) {
492 cache64_unroll32(start,Hit_Writeback_Inv_SD);
493 start += 0x800;
499 unsigned long start = page;
502 while (start < end) {
503 cache64_unroll32(start,Index_Writeback_Inv_SD);
504 start += 0x800;
536 unsigned long start = KSEG0;
539 while (start < end) {
540 cache128_unroll32(start,Index_Writeback_Inv_SD);
541 start += 0x1000;