Lines Matching refs:cs
36 static void ph_command(struct IsdnCardState *cs, unsigned int command);
37 static inline void cic_int(struct IsdnCardState *cs);
39 static void dbusy_timer_handler(struct IsdnCardState *cs);
40 static void ipacx_new_ph(struct IsdnCardState *cs);
41 static void dch_bh(struct IsdnCardState *cs);
42 static void dch_sched_event(struct IsdnCardState *cs, int event);
43 static void dch_empty_fifo(struct IsdnCardState *cs, int count);
44 static void dch_fill_fifo(struct IsdnCardState *cs);
45 static inline void dch_int(struct IsdnCardState *cs);
46 static void __devinit dch_setstack(struct PStack *st, struct IsdnCardState *cs);
47 static void __devinit dch_init(struct IsdnCardState *cs);
52 static void bch_int(struct IsdnCardState *cs, u_char hscx);
55 static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
57 static void __devinit bch_init(struct IsdnCardState *cs, int hscx);
58 static void __init clear_pending_ints(struct IsdnCardState *cs);
64 ph_command(struct IsdnCardState *cs, unsigned int command)
66 if (cs->debug &L1_DEB_ISAC)
67 debugl1(cs, "ph_command (%#x) in (%#x)", command,
68 cs->dc.isac.ph_state);
72 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
79 cic_int(struct IsdnCardState *cs)
83 event = cs->readisac(cs, IPACX_CIR0) >> 4;
84 if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
88 cs->dc.isac.ph_state = event;
89 dch_sched_event(cs, D_L1STATECHANGE);
102 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
108 if (cs->debug &DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
109 if (cs->debug &DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
110 if (cs->tx_skb) {
111 skb_queue_tail(&cs->sq, skb);
113 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
116 cs->tx_skb = skb;
117 cs->tx_cnt = 0;
119 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0);
121 dch_fill_fifo(cs);
126 if (cs->tx_skb) {
127 if (cs->debug & L1_DEB_WARN)
128 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
129 skb_queue_tail(&cs->sq, skb);
132 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
133 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
134 cs->tx_skb = skb;
135 cs->tx_cnt = 0;
137 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
139 dch_fill_fifo(cs);
144 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL");
146 if (!cs->tx_skb) {
155 ph_command(cs, IPACX_CMD_TIM);
159 ph_command(cs, IPACX_CMD_AR8);
163 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
164 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
165 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
166 cda2_cr = cs->readisac(cs, IPACX_CDA2_CR);
168 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
171 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
174 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14);
177 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
182 skb_queue_purge(&cs->rq);
183 skb_queue_purge(&cs->sq);
184 if (cs->tx_skb) {
185 dev_kfree_skb_any(cs->tx_skb);
186 cs->tx_skb = NULL;
188 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
189 del_timer(&cs->dbusytimer);
193 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr);
201 dbusy_timer_handler(struct IsdnCardState *cs)
206 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
207 rbchd = cs->readisac(cs, IPACX_RBCHD);
208 stard = cs->readisac(cs, IPACX_STARD);
209 if (cs->debug)
210 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
212 set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
213 for (st = cs->stlist; st; st = st->next) {
218 clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
219 if (cs->tx_skb) {
220 dev_kfree_skb_any(cs->tx_skb);
221 cs->tx_cnt = 0;
222 cs->tx_skb = NULL;
225 debugl1(cs, "D-Channel Busy no skb");
227 cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
236 ipacx_new_ph(struct IsdnCardState *cs)
238 switch (cs->dc.isac.ph_state) {
240 ph_command(cs, IPACX_CMD_DI);
241 l1_msg(cs, HW_RESET | INDICATION, NULL);
245 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
249 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
253 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
257 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
261 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
265 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
269 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
281 dch_bh(struct IsdnCardState *cs)
285 if (!cs) return;
287 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
288 if (cs->debug) debugl1(cs, "D-Channel Busy cleared");
289 for (st = cs->stlist; st; st = st->next) {
294 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) {
295 DChannel_proc_rcv(cs);
298 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) {
299 DChannel_proc_xmt(cs);
302 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
303 ipacx_new_ph(cs);
311 dch_sched_event(struct IsdnCardState *cs, int event)
313 set_bit(event, &cs->event);
314 queue_task(&cs->tqueue, &tq_immediate);
322 dch_empty_fifo(struct IsdnCardState *cs, int count)
327 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
328 debugl1(cs, "dch_empty_fifo()");
331 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
332 if (cs->debug &L1_DEB_WARN)
333 debugl1(cs, "dch_empty_fifo() incoming message too large");
334 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
335 cs->rcvidx = 0;
339 ptr = cs->rcvbuf + cs->rcvidx;
340 cs->rcvidx += count;
344 cs->readisacfifo(cs, ptr, count);
345 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
348 if (cs->debug &L1_DEB_ISAC_FIFO) {
349 char *t = cs->dlog;
353 debugl1(cs, cs->dlog);
361 dch_fill_fifo(struct IsdnCardState *cs)
367 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
368 debugl1(cs, "dch_fill_fifo()");
370 if (!cs->tx_skb) return;
371 count = cs->tx_skb->len;
383 ptr = cs->tx_skb->data;
384 skb_pull(cs->tx_skb, count);
385 cs->tx_cnt += count;
386 cs->writeisacfifo(cs, ptr, count);
387 cs->writeisac(cs, IPACX_CMDRD, cmd);
390 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
391 debugl1(cs, "dch_fill_fifo dbusytimer running");
392 del_timer(&cs->dbusytimer);
394 init_timer(&cs->dbusytimer);
395 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
396 add_timer(&cs->dbusytimer);
399 if (cs->debug &L1_DEB_ISAC_FIFO) {
400 char *t = cs->dlog;
404 debugl1(cs, cs->dlog);
412 dch_int(struct IsdnCardState *cs)
419 istad = cs->readisac(cs, IPACX_ISTAD);
425 rstad = cs->readisac(cs, IPACX_RSTAD);
428 if (cs->debug &L1_DEB_WARN)
429 debugl1(cs, "dch_int(): invalid frame");
431 if (cs->debug &L1_DEB_WARN)
432 debugl1(cs, "dch_int(): RDO");
434 if (cs->debug &L1_DEB_WARN)
435 debugl1(cs, "dch_int(): CRC error");
436 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
438 count = cs->readisac(cs, IPACX_RBCLD);
442 dch_empty_fifo(cs, count);
445 if ((count = cs->rcvidx) > 0) {
446 cs->rcvidx = 0;
450 memcpy(skb_put(skb, count), cs->rcvbuf, count);
451 skb_queue_tail(&cs->rq, skb);
456 cs->rcvidx = 0;
457 dch_sched_event(cs, D_RCVBUFREADY);
461 dch_empty_fifo(cs, D_FIFO_SIZE);
465 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
466 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
470 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
471 del_timer(&cs->dbusytimer);
472 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
473 dch_sched_event(cs, D_CLEARBUSY);
474 if (cs->tx_skb) {
475 if (cs->tx_skb->len) {
476 dch_fill_fifo(cs);
480 dev_kfree_skb_irq(cs->tx_skb);
481 cs->tx_skb = NULL;
482 cs->tx_cnt = 0;
485 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
486 cs->tx_cnt = 0;
487 dch_fill_fifo(cs);
490 dch_sched_event(cs, D_XMTBUFREADY);
496 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): XDU");
497 if (cs->tx_skb) {
498 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit
499 cs->tx_cnt = 0;
500 dch_fill_fifo(cs);
503 debugl1(cs, "ISAC XDU no skb");
511 dch_setstack(struct PStack *st, struct IsdnCardState *cs)
519 dch_init(struct IsdnCardState *cs)
523 cs->tqueue.routine = (void *)(void *) dch_bh;
524 cs->setstack_d = dch_setstack;
526 cs->dbusytimer.function = (void *) dbusy_timer_handler;
527 cs->dbusytimer.data = (long) cs;
528 init_timer(&cs->dbusytimer);
530 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
531 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
532 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
533 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
617 struct IsdnCardState *cs;
621 cs = bcs->cs;
623 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
624 debugl1(cs, "bch_empty_fifo()");
628 if (cs->debug &L1_DEB_WARN)
629 debugl1(cs, "bch_empty_fifo() incoming packet too large");
630 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
640 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
641 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
647 if (cs->debug &L1_DEB_HSCX_FIFO) {
652 debugl1(cs, bcs->blog);
662 struct IsdnCardState *cs;
667 cs = bcs->cs;
668 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
669 debugl1(cs, "bch_fill_fifo()");
690 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
691 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
694 if (cs->debug &L1_DEB_HSCX_FIFO) {
699 debugl1(cs, bcs->blog);
707 bch_int(struct IsdnCardState *cs, u_char hscx)
715 bcs = cs->bcs + hscx;
716 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
723 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
726 if (cs->debug &L1_DEB_WARN)
727 debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
729 if (cs->debug &L1_DEB_WARN)
730 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
732 if (cs->debug &L1_DEB_WARN)
733 debugl1(cs, "bch_int() B-%d: CRC error", hscx);
734 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
737 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) &(B_FIFO_SIZE-1);
741 if (cs->debug &L1_DEB_HSCX_FIFO)
742 debugl1(cs, "bch_int Frame %d", count);
772 if (cs->debug &L1_DEB_WARN)
773 debugl1(cs, "bch_int() B-%d: RFO error", hscx);
774 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES
814 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES
815 if (cs->debug &L1_DEB_WARN)
816 debugl1(cs, "bch_int() B-%d XDU error", hscx);
826 struct IsdnCardState *cs = bcs->cs;
830 if (cs->debug & L1_DEB_HSCX)
831 debugl1(cs, "mode_bch() switch B-% mode %d chan %d", hscx, mode, bc);
838 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
839 cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
843 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
844 cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
849 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off
850 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj.
851 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off
852 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
855 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode
856 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000
857 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
858 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
861 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0
862 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
863 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
864 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
897 bch_open_state(struct IsdnCardState *cs, struct BCState *bcs)
943 bch_init(struct IsdnCardState *cs, int hscx)
945 cs->bcs[hscx].BC_SetStack = bch_setstack;
946 cs->bcs[hscx].BC_Close = bch_close_state;
947 cs->bcs[hscx].hw.hscx.hscx = hscx;
948 cs->bcs[hscx].cs = cs;
949 bch_mode(cs->bcs + hscx, 0, hscx);
961 interrupt_ipacx(struct IsdnCardState *cs)
965 while ((ista = cs->readisac(cs, IPACX_ISTA))) {
969 if (ista &0x80) bch_int(cs, 0); // B channel interrupts
970 if (ista &0x40) bch_int(cs, 1);
972 if (ista &0x01) dch_int(cs); // D channel
973 if (ista &0x10) cic_int(cs); // Layer 1 state
981 clear_pending_ints(struct IsdnCardState *cs)
986 cs->writeisac(cs, IPACX_MASK, 0xff);
987 cs->writeisac(cs, IPACX_MASKD, 0xff);
988 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff);
989 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff);
991 ista = cs->readisac(cs, IPACX_ISTA);
992 if (ista &0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB);
993 if (ista &0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB);
994 if (ista &0x10) cs->readisac(cs, IPACX_CIR0);
995 if (ista &0x01) cs->readisac(cs, IPACX_ISTAD);
1003 init_ipacx(struct IsdnCardState *cs, int part)
1009 clear_pending_ints(cs);
1010 bch_init(cs, 0);
1011 bch_init(cs, 1);
1012 dch_init(cs);
1015 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
1016 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
1017 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
1018 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
1021 cs->writeisac(cs, IPACX_CMDRD, 0x41);
1022 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41);
1023 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41);
1024 ph_command(cs, IPACX_CMD_RES);