Lines Matching refs:value32
347 LM_UINT32 value32;
362 value32 = REG_RD( pDevice, Nvram.SwArb );
363 if( value32 & SW_ARB_GNT1 )
401 LM_UINT32 value32;
410 value32 = REG_RD( pDevice, Grc.EepromAddr );
411 if( value32 & SEEPROM_ADDR_COMPLETE )
438 LM_UINT32 value32;
450 value32 = REG_RD( pDevice, Nvram.Cmd );
451 if( value32 & NVRAM_CMD_DONE )
478 LM_UINT32 value32;
486 value32 = REG_RD( pDevice, Grc.EepromAddr );
487 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
489 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
492 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
495 value32 = REG_RD( pDevice, Grc.EepromData );
498 *data = MM_SWAP_LE32( value32 );
517 LM_UINT32 value32;
548 value32 = REG_RD( pDevice, Nvram.ReadData );
556 *data = MM_SWAP_BE32( value32 );
572 LM_UINT32 value32;
582 value32 = 0;
587 status = LM_NvramRead(pDevice, 0, &value32);
593 value32 = MM_SWAP_BE32(value32);
594 if( value32 != 0x669955aa )
606 status = LM_NvramRead(pDevice, cursize, &value32);
613 value32 = MM_SWAP_BE32(value32);
614 if( value32 == 0x669955aa )
638 LM_UINT32 value32;
643 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
644 value32 |= NVRAM_READ_COMMAND(0x57);
645 REG_WR( pDevice, Nvram.Config3, value32 );
649 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
655 switch( value32 & 0x3c )
688 LM_UINT32 value32;
693 value32 = config1 | FLASH_PASS_THRU_MODE;
694 REG_WR( pDevice, Nvram.Config1, value32 );
718 value32 = REG_RD(pDevice, Nvram.ReadData);
726 value32 = REG_RD(pDevice, Nvram.ReadData) & 0xff;
727 switch( value32 )
763 LM_UINT32 value32;
768 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
769 value32 |= NVRAM_READ_COMMAND(0xab);
770 REG_WR( pDevice, Nvram.Config3, value32 );
774 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
781 switch( value32 & 0xff )
808 LM_UINT32 value32;
821 value32 = REG_RD( pDevice, Nvram.NvmAccess );
822 value32 |= NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE;
823 REG_WR( pDevice, Nvram.NvmAccess, value32 );
854 value32 = REG_RD( pDevice, Nvram.NvmAccess );
855 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
856 REG_WR( pDevice, Nvram.NvmAccess, value32 );
867 LM_UINT32 value32;
869 value32 = REG_RD(pDevice, Nvram.Config1);
871 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
891 LM_UINT32 value32;
893 value32 = REG_RD(pDevice, Nvram.Config1);
895 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
903 switch( value32 & FLASH_PART_5750_TYPEMASK )
943 LM_UINT32 value32;
947 value32 = REG_RD(pDevice, Nvram.Config1);
949 if(value32 & BIT_27)
952 switch( value32 & FLASH_PART_5752_TYPEMASK )
1030 switch( value32 & FLASH_PART_5752_PAGEMASK )
1178 LM_UINT32 value32;
1203 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1204 value32 |= NVRAM_ACCESS_ENABLE;
1205 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1215 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1216 value32 &= ~NVRAM_ACCESS_ENABLE;
1217 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1241 LM_UINT32 value32;
1250 value32 = offset & 0x3;
1251 if( value32 )
1253 bytecnt = sizeof(LM_UINT32) - value32;
1254 offset -= value32;
1255 srcptr = (LM_UINT8 *)(&value32) + value32;
1260 srcptr = (LM_UINT8 *)(&value32);
1271 status = LM_NVRAM_Read_UINT32( pDevice, offset, &value32 );
1275 status = LM_EEPROM_Read_UINT32( pDevice, offset, &value32 );
1303 LM_UINT32 value32;
1360 value32 = REG_RD( pDevice, Grc.LocalCtrl );
1361 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1369 value32 = offset & 0x3;
1370 if( value32 )
1378 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1379 bytecnt = sizeof(LM_UINT32) - value32;
1380 value32 = subword1;
1384 dstptr = (LM_UINT8 *)(&value32);
1386 value32 = subword2;
1390 dstptr = (LM_UINT8 *)(&value32);
1408 value32 = MM_SWAP_LE32(value32);
1411 REG_WR( pDevice, Grc.EepromData, value32 );
1416 value32 = REG_RD( pDevice, Grc.EepromAddr );
1417 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
1419 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
1422 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
1458 LM_UINT32 value32;
1475 value32 = REG_RD( pDevice, Nvram.Config2 );
1476 value32 &= ~(NVRAM_STATUS_COMMAND( NVRAM_COMMAND_MASK ) |
1478 value32 |= NVRAM_STATUS_COMMAND( SAIFUN_SA25F0XX_READ_STATUS_CMD ) |
1480 REG_WR( pDevice, Nvram.Config2, value32 );
1483 value32 = REG_RD( pDevice, Nvram.Config3 );
1484 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1485 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( SAIFUN_SA25F0XX_PAGE_WRITE_CMD );
1486 REG_WR( pDevice, Nvram.Config3, value32 );
1489 value32 = REG_RD( pDevice, Nvram.Write1 );
1490 value32 &= ~NVRAM_WRITE1_WRENA_CMD( NVRAM_COMMAND_MASK );
1491 value32 |= NVRAM_WRITE1_WRENA_CMD( SAIFUN_SA25F0XX_WRENA_CMD );
1492 REG_WR( pDevice, Nvram.Write1, value32 );
1578 value32 = *((LM_UINT32 *)(&pDevice->flashbuffer[i]));
1579 value32 = MM_SWAP_BE32( value32 );
1585 REG_WR( pDevice, Nvram.WriteData, value32 );
1631 LM_UINT32 value32;
1652 value32 = REG_RD(pDevice, Nvram.Config1);
1653 value32 &= ~FLASH_STATUS_BITS_MASK;
1654 REG_WR( pDevice, Nvram.Config1, value32 );
1657 value32 = NVRAM_STATUS_COMMAND( ST_M45PEX0_READ_STATUS_CMD ) |
1659 REG_WR( pDevice, Nvram.Config2, value32 );
1662 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1663 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1664 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ST_M45PEX0_PAGE_PRGM_CMD );
1665 REG_WR( pDevice, Nvram.Config3, value32 );
1668 value32 = NVRAM_WRITE1_WRENA_CMD( ST_M45PEX0_WRENA_CMD ) |
1670 REG_WR( pDevice, Nvram.Write1, value32 );
1689 value32 = REG_RD(pDevice, Nvram.Config1);
1690 value32 |= FLASH_STATUS_BITS_MASK;
1691 REG_WR( pDevice, Nvram.Config1, value32 );
1694 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1695 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1696 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ATMEL_AT45DB0X1B_BUFFER_WRITE_CMD );
1697 REG_WR( pDevice, Nvram.Config3, value32 );
1752 value32 = offset & 0x3;
1753 if( value32 )
1761 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1762 bytecnt = sizeof(LM_UINT32) - value32;
1763 value32 = subword1;
1767 dstptr = (LM_UINT8 *)(&value32);
1769 value32 = subword2;
1773 dstptr = (LM_UINT8 *)(&value32);
1791 value32 = MM_SWAP_BE32(value32);
1794 REG_WR(pDevice, Nvram.WriteData, value32);
1890 LM_UINT32 value32;
1921 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1922 value32 |= (NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1923 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1935 value32 = REG_RD(pDevice, Grc.LocalCtrl);
1936 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1943 value32 = REG_RD(pDevice, Grc.Mode);
1944 value32 |= GRC_MODE_NVRAM_WRITE_ENABLE;
1945 REG_WR(pDevice, Grc.Mode, value32);
1957 value32 = REG_RD(pDevice, Grc.Mode);
1958 value32 &= ~GRC_MODE_NVRAM_WRITE_ENABLE;
1959 REG_WR(pDevice, Grc.Mode, value32);
1976 value32 = REG_RD(pDevice, Nvram.NvmAccess);
1977 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1978 REG_WR(pDevice, Nvram.NvmAccess, value32);
2153 LM_UINT32 value32, offset, asf_offset, ver_offset, start_addr;
2156 if (LM_NvramRead(pDevice, 0x0, &value32) != LM_STATUS_SUCCESS)
2158 value32 = MM_SWAP_BE32(value32);
2159 if (value32 != 0x669955aa)
2164 if (LM_NvramRead(pDevice, offset, &value32) != LM_STATUS_SUCCESS)
2166 value32 = MM_SWAP_BE32(value32) & 0xff000000;
2167 if (value32 == 0x1000000)
2208 if (LM_NvramRead(pDevice, ver_offset + i, &value32) != LM_STATUS_SUCCESS)
2210 memcpy(&(pDevice->IPMICodeVer[i]), &value32, sizeof(value32));
9746 LM_UINT32 value32;
9775 value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
9778 MM_SWAP_LE32(value32));
9790 value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
9792 value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
9794 if ((value32 & 0xffff) == dma_desc_addr)