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d2185e79 |
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02-Feb-2023 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for PSFP flow-meters Add support for configuring PSFP flow-meters (IEEE 802.1Q-2018, 8.6.5.1.3). The VCAP CLM (VCAP IS0 ingress classifier) classifies streams, identified by ISDX (Ingress Service Index, frame metadata), and maps ISDX to flow-meters. SDLB's provide the flow-meter parameters. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1db82abf |
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02-Feb-2023 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for service policers Add initial API for configuring policers. This patch add support for service policers. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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9bf50889 |
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02-Feb-2023 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for Service Dual Leacky Buckets Add support for Service Dual Leacky Buckets (SDLB), used to implement PSFP flow-meters. Buckets are linked together in a leak chain of a leak group. Leak groups a preconfigured to serve buckets within a certain rate interval. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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bb535c0d |
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02-Feb-2023 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add resource pools Add resource pools and accessor functions. These pools can be queried by the driver, whenever a finite resource is required. Some resources can be reused, in which case an index and a reference count is used to keep track of users. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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e0305cc1 |
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17-Nov-2022 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Add VCAP debugFS support Add a debugFS root folder for Sparx5 and add a vcap folder underneath with the VCAP instances and the ports Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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67456717 |
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08-Nov-2022 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Add tc matchall filter and enable VCAP lookups Use a tc matchall rule with a goto action to the VCAP specific chain to enable the VCAP lookups. If the matchall rule is removed the VCAP lookups will be disabled again using its cookie as lookup to find the VCAP instance. To enable the Sparx5 IS2 VCAP on eth0 you would use this command: tc filter add dev eth0 ingress prio 5 handle 5 matchall \ skip_sw action goto chain 8000000 as the first lookup in IS2 has chain id 8000000 Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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92ef3d01 |
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01-Nov-2022 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for offloading pcp table Add new registers and functions to support offload of pcp app entries. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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c9da1ac1 |
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20-Oct-2022 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Adding initial tc flower support for VCAP API This adds initial TC flower filter support to Sparx5 for the IS2 VCAP. The support consists of the source and destination MAC addresses, and the trap and pass actions. This is how you can create a rule that test the functionality: tc qdisc add dev eth0 clsact tc filter add dev eth0 ingress chain 8000000 prio 10 handle 10 \ protocol all flower skip_sw \ dst_mac 0a:0b:0c:0d:0e:0f \ src_mac 2:0:0:0:0:1 \ action trap The IS2 chains in Sparx5 are assigned like this: - chain 8000000: IS2 Lookup 0 - chain 8100000: IS2 Lookup 1 - chain 8200000: IS2 Lookup 2 - chain 8300000: IS2 Lookup 3 Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Tested-by: Casper Andersson <casper.casan@gmail.com> Reviewed-by: Casper Andersson <casper.casan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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e8145e06 |
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20-Oct-2022 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Adding IS2 VCAP model to VCAP API This provides the Sparx5 Ingress Stage 2 (IS2) model and adds it to the VCAP control instance that will be provided to the VCAP API. The Sparx5 IS2 C code model is generated from the Sparx5 RTL design model. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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8beef08f |
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20-Oct-2022 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Adding initial VCAP API support This provides the initial VCAP API framework and Sparx5 specific VCAP implementation. When the Sparx5 Switchdev driver is initialized it will also initialize its VCAP module, and this hooks up the concrete Sparx5 VCAP model to the VCAP API, so that the VCAP API knows what VCAP instances are available. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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ab0e493e |
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19-Sep-2022 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for offloading mqprio qdisc Add support for offloading mqprio qdisc to sparx5 switch. The offloaded mqprio qdisc currently does nothing by itself, but serves as an attachment point for other qdiscs (tbf, ets etc.) Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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65ec1bbe |
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19-Sep-2022 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add tc setup hook Add tc setup hook for QoS features. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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af9b45d0 |
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21-Mar-2022 |
Casper Andersson <casper.casan@gmail.com> |
net: sparx5: Add arbiter for managing PGID table The PGID (Port Group ID) table holds port masks for different purposes. The first 72 are reserved for port destination masks, flood masks, and CPU forwarding. The rest are shared between multicast, link aggregation, and virtualization profiles. The GLAG area is reserved to not be used by anything else, since it is a subset of the MCAST area. The arbiter keeps track of which entries are in use. You can ask for a free ID or give back one you are done using. Signed-off-by: Casper Andersson <casper.casan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0933bd04 |
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03-Mar-2022 |
Horatiu Vultur <horatiu.vultur@microchip.com> |
net: sparx5: Add support for ptp clocks The sparx5 has 3 PHC. Enable each of them, for now all the timestamping is happening on the first PHC. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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10615907 |
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19-Aug-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: switchdev: adding frame DMA functionality This add frame DMA functionality to the Sparx5 platform. Ethernet frames can be extracted or injected autonomously to or from the device’s DDR3/DDR3L memory and/or PCIe memory space. Linked list data structures in memory are used for injecting or extracting Ethernet frames. The FDMA generates interrupts when frame extraction or injection is done and when the linked lists need updating. The FDMA implements two extraction channels, one per switch core port towards the VCore CPU system and a total of six injection channels. Extraction channels are mapped one-to-one to the CPU ports, while injection channels can be individually assigned to any CPU port. - FDMA channel 0 through 5 corresponds to CPU port 0 injection direction FDMA_CH_CFG[channel].CH_INJ_PORT is set to 0. - FDMA channel 0 through 5 corresponds to CPU port 1 injection direction when FDMA_CH_CFG[channel].CH_INJ_PORT is set to 1. - FDMA channel 6 corresponds to CPU port 0 extraction direction. - FDMA channel 7 corresponds to CPU port 1 extraction direction. The FDMA implements a strict priority scheme among channels. Extraction channels are prioritized over injection channels and secondarily channels with higher channel number are prioritized over channels with lower number. On the other hand, ports are being served on an equal-bandwidth principle both on injection and extraction directions. The equal-bandwidth principle will not force an equal bandwidth. Instead, it ensures that the ports perform at their best considering the operating conditions. When more than one injection channel is enabled for injection on the same CPU port, priority determines which channel can inject data. Ownership is re-arbitrated on frame boundaries. The FDMA processes linked lists of DMA Control Block Structures (DCBs). The DCBs have the same basic structure for both injection and extraction. A DCB must be placed on a 64-bit word-aligned address in memory. Each DCB has a per-channel configurable amount of associated data blocks in memory, where the frame data is stored. The data blocks that are used by extraction channels must be placed on 64-bit word aligned addresses in memory, and their length must be a multiple of 128 bytes. A DCB carries the pointer to the next DCB of the linked list, the INFO word which holds information for the DCB, and a pair of status word and memory pointer for every data block that it is associated with. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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af4b1102 |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add ethtool configuration and statistics support This adds statistic counters for the network interfaces provided by the driver. It also adds CPU port counters (which are not exposed by ethtool). This also adds support for configuring the network interface parameters via ethtool: speed, duplex, aneg etc. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0a9d48ad |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add calendar bandwidth allocation support This configures the Sparx5 calendars according to the bandwidth requested in the Device Tree nodes. It also checks if the total requested bandwidth is within the specs of the detected Sparx5 models limits. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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d6fce514 |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add switching support This adds SwitchDev support by hardware offloading the software bridge. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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78eab33b |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add vlan support This adds Sparx5 VLAN support. Sparx5 has more VLAN features than provided here, but these will be added in later series. For now we only add the basic L2 features. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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b37a1bae |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add mactable support This adds the Sparx5 MAC tables: listening for MAC table updates and updating on request. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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946e7fd5 |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add port module support This add configuration of the Sparx5 port module instances. Sparx5 has in total 65 logical ports (denoted D0 to D64) and 33 physical SerDes connections (S0 to S32). The 65th port (D64) is fixed allocated to SerDes0 (S0). The remaining 64 ports can in various multiplexing scenarios be connected to the remaining 32 SerDes using QSGMII, or USGMII or USXGMII extenders. 32 of the ports can have a 1:1 mapping to the 32 SerDes. Some additional ports (D65 to D69) are internal to the device and do not connect to port modules or SerDes macros. For example, internal ports are used for frame injection and extraction to the CPU queues. The 65 logical ports are split up into the following blocks. - 13 x 5G ports (D0-D11, D64) - 32 x 2G5 ports (D16-D47) - 12 x 10G ports (D12-D15, D48-D55) - 8 x 25G ports (D56-D63) Each logical port supports different line speeds, and depending on the speeds supported, different port modules (MAC+PCS) are needed. A port supporting 5 Gbps, 10 Gbps, or 25 Gbps as maximum line speed, will have a DEV5G, DEV10G, or DEV25G module to support the 5 Gbps, 10 Gbps (incl 5 Gbps), or 25 Gbps (including 10 Gbps and 5 Gbps) speeds. As well as, it will have a shadow DEV2G5 port module to support the lower speeds (10/100/1000/2500Mbps). When a port needs to operate at lower speed and the shadow DEV2G5 needs to be connected to its corresponding SerDes Not all interface modes are supported in this series, but will be added at a later stage. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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f3cad261 |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add hostmode with phylink support This patch adds netdevs and phylink support for the ports in the switch. It also adds register based injection and extraction for these ports. Frame DMA support for injection and extraction will be added in a later series. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3cfa11ba |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add the basic sparx5 driver This adds the Sparx5 basic SwitchDev driver framework with IO range mapping, switch device detection and core clock configuration. Support for ports, phylink, netdev, mactable etc. are in the following patches. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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