#
18397519 |
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23-Feb-2024 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Add A702 support The A702 is a weird mix of 600 and 700 series.. Perhaps even a testing ground for some A7xx features with good ol' A6xx silicon. It's basically A610 that's been beefed up with some new registers and hw features (like APRIV!), that was then cut back in size, memory bus and some other ways. Add support for it, tested with QCM2290 / RB1. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579752/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
d2bcca0c |
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15-Feb-2024 |
Neil Armstrong <neil.armstrong@linaro.org> |
drm/msm: add support for A750 GPU Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/578693/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
3d6ab124 |
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21-Jan-2024 |
Luca Weiss <luca@z3ntu.xyz> |
drm/msm/adreno: Add A305B support Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC. Previously this was mistakenly claimed to be supported but using wrong a configuration. In MSM8226v1 there's also a A305B but with chipid 0x03000510 which should work with the same configuration but due to lack of hardware for testing this is not added. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: David Heidelberg <david@ixit.cz> Patchwork: https://patchwork.freedesktop.org/patch/575274/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
a7165277 |
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18-Feb-2024 |
Danila Tikhonov <danila@jiaxyga.com> |
drm/msm/adreno: Add support for SM7150 SoC machine SM7150 has 5 power levels which correspond to 5 speed-bin values: 0, 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up to zero decimal places. Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn). Add this as machine = "qcom,sm7150", because speed-bin values are different from atoll (sc7180/sm7125). Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/578902/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
3e6688fd |
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30-Nov-2023 |
Bjorn Andersson <quic_bjorande@quicinc.com> |
drm/msm/adreno: Fix A680 chip id The only A680 referenced from DeviceTree is patch level 1, which since commit '90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU")' isn't a known chip id. Correct the chip id to allow the A680 to be recognized again. Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/569839/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
35963cf2 |
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30-Oct-2023 |
Matthew Brost <matthew.brost@intel.com> |
drm/sched: Add drm_sched_wqueue_* helpers Add scheduler wqueue ready, stop, and start helpers to hide the implementation details of the scheduler from the drivers. v2: - s/sched_wqueue/sched_wqueue (Luben) - Remove the extra white line after the return-statement (Luben) - update drm_sched_wqueue_ready comment (Luben) Cc: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Link: https://lore.kernel.org/r/20231031032439.1558703-2-matthew.brost@intel.com Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
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#
1d524571 |
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26-Sep-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Add A635 speedbin 0xac (A643) Downstream calls this the "speedbin 1", but that number is already occupied. Use index two. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559607/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
3e7042ba |
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26-Sep-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Add ZAP firmware name to A635 Some (many?) devices with A635 expect a ZAP shader to be loaded. Set the file name to allow for that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559605/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
beb35423 |
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25-Aug-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Fix SM6375 GPU ID SM6375 comes with a patchlevel=1. Fix the chipid up to reflect that. Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/554527/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
1f8c29e8 |
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25-Sep-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add A740 support A740 builds upon the A730 IP, shuffling some values and registers around. More differences will appear when things like BCL are implemented. adreno_is_a740_family is added in preparation for more A7xx GPUs, the logic checks will be valid resulting in smaller diffs. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559291/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
9588d2f8 |
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25-Sep-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add A730 support Add support for Adreno 730, also known as GEN7_0_x, found on SM8450. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559290/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
01790d5e |
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07-May-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
drm/msm: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert the msm drm drivers from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230507162616.1368908-32-u.kleine-koenig@pengutronix.de
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#
cb0aacde |
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19-Jun-2023 |
Juerg Haefliger <juerg.haefliger@canonical.com> |
drm/msm/adreno: Add missing MODULE_FIRMWARE macros The driver references some firmware files that don't have corresponding MODULE_FIRMWARE macros and thus won't be listed via modinfo. Fix that. Signed-off-by: Juerg Haefliger <juerg.haefliger@canonical.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Joel Fernandes (Google) <joel@joelfernandes.org> Patchwork: https://patchwork.freedesktop.org/patch/543290/ [rob: drop a690_gmu.bin as a690 is using same fw as a660 now] Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
18ff50e5 |
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11-Aug-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/a690: Switch to a660_gmu.bin There isn't actually a a690_gmu.bin. But it appears that the normal a660_gmu.bin works fine. Normally all the devices within a sub- generation (or "family") will use the same fw, and a690 is in the a660 family. Signed-off-by: Rob Clark <robdclark@chromium.org> Fixes: 5e7665b5e484 ("drm/msm/adreno: Add Adreno A690 support") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/552406/
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#
90b593ce |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Switch to chip-id for identifying GPU Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549782/
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#
47bd37f9 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Move adreno info to config Let's just stash it in adreno_platform_config rather than looking it up in N different places. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549777/
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#
8825f596 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Add helper for formating chip-id This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549774/
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#
67133dc0 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Add adreno family Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id. v2: Fix is_a2xx() typo Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549773/
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#
c928a05e |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Move speedbin mapping to device table This simplifies the code. v2: Use a table of structs instead of flat uint32_t[] Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549769/
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#
f30a648d |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Allow SoC specific gpu device table entries There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549767/
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#
155668ef |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Use quirk to identify cached-coherent support It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549765/
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#
459f9e26 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Use quirk identify hw_apriv Rather than just open coding a list of gpu-id matches. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549764/
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#
832ee64d |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Remove GPU name No real need to have marketing names in the kernel. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549757/
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#
317ab1b9 |
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04-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/a690: Remove revn and name These fields are deprecated. But any userspace new enough to support a690 also knows how to identify the GPU based on chip-id. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545552/
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#
e7fc9398 |
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15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add A610 support A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542779/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
9bad3760 |
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15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations A610 and A619_holi don't support the feature. Disable it to make the GPU stop crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature it. Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542774/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
5e7665b5 |
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30-May-2023 |
Bjorn Andersson <andersson@kernel.org> |
drm/msm/adreno: Add Adreno A690 support Introduce support for the Adreno A690, found in Qualcomm SC8280XP. Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/540335/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
3eeca5e5 |
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30-Mar-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: adreno_gpu: Use suspend() instead of idle() on load error The adreno_load_gpu() path is guarded by an error check on adreno_load_fw(). This function is responsible for loading Qualcomm-only-signed binaries (e.g. SQE and GMU FW for A6XX), but it does not take the vendor-signed ZAP blob into account. By embedding the SQE (and GMU, if necessary) firmware into the initrd/kernel, we can trigger and unfortunate path that would not bail out early and proceed with gpu->hw_init(). That will fail, as the ZAP loader path will not find the firmware and return back to adreno_load_gpu(). This error path involves pm_runtime_put_sync() which then calls idle() instead of suspend(). This is suboptimal, as it means that we're not going through the clean shutdown sequence. With at least A619_holi, this makes the GPU not wake up until it goes through at least one more start-fail-stop cycle. The pm_runtime_put_sync that appears in the error path actually does not guarantee that because of the earlier enabling of runtime autosuspend. Fix that by using pm_runtime_put_sync_suspend to force a clean shutdown. Test cases: 1. All firmware baked into kernel 2. error loading ZAP fw in initrd -> load from rootfs at DE start Both succeed on A619_holi (SM6375) and A630 (SDM845). Fixes: 0d997f95b70f ("drm/msm/adreno: fix runtime PM imbalance at gpu load") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/530001/ Link: https://lore.kernel.org/r/20230330231517.2747024-1-konrad.dybcio@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
8ead9678 |
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20-Mar-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/gpu: Move BO allocation out of hw_init These allocations are only done the first (successful) time through hw_init() so they won't actually happen in the job_run() path. But lockdep doesn't know this. So dis-entangle them from the hw_init() path. Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/527852/ Link: https://lore.kernel.org/r/20230320144356.803762-14-robdclark@gmail.com
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#
eaa667db |
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03-Mar-2023 |
Johan Hovold <johan+linaro@kernel.org> |
drm/msm/adreno: clean up component ops indentation Clean up the component ops initialisers which were indented one level too far. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/524973/ Link: https://lore.kernel.org/r/20230303164807.13124-5-johan+linaro@kernel.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
db7662d0 |
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03-Mar-2023 |
Johan Hovold <johan+linaro@kernel.org> |
drm/msm/adreno: drop bogus pm_runtime_set_active() The runtime PM status can only be updated while runtime PM is disabled. Drop the bogus pm_runtime_set_active() call that was made after enabling runtime PM and which (incidentally but correctly) left the runtime PM status set to 'suspended'. Fixes: 2c087a336676 ("drm/msm/adreno: Load the firmware before bringing up the hardware") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/524972/ Link: https://lore.kernel.org/r/20230303164807.13124-4-johan+linaro@kernel.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
0d997f95 |
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03-Mar-2023 |
Johan Hovold <johan+linaro@kernel.org> |
drm/msm/adreno: fix runtime PM imbalance at gpu load A recent commit moved enabling of runtime PM to GPU load time (first open()) but failed to update the error paths so that runtime PM is disabled if initialisation of the GPU fails. This would trigger a warning about the unbalanced disable count on the next open() attempt. Note that pm_runtime_put_noidle() is sufficient to balance the usage count when pm_runtime_put_sync() fails (and is chosen over pm_runtime_resume_and_get() for consistency reasons). Fixes: 4b18299b3365 ("drm/msm/adreno: Defer enabling runpm until hw_init()") Cc: stable@vger.kernel.org # 6.0 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/524971/ Link: https://lore.kernel.org/r/20230303164807.13124-3-johan+linaro@kernel.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
8d260047 |
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23-Feb-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Enable optional icc voting from OPP tables Add the dev_pm_opp_of_find_icc_paths() call to let the OPP framework handle bus voting as part of power level setting. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/523787/ Link: https://lore.kernel.org/r/20230223-topic-opp-v3-7-5f22163cd1df@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
6153c443 |
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21-Feb-2023 |
Johan Hovold <johan+linaro@kernel.org> |
drm/msm/adreno: fix runtime PM imbalance at unbind A recent commit moved enabling of runtime PM from adreno_gpu_init() to adreno_load_gpu() (called on first open()), which means that unbind() may now be called with runtime PM disabled in case the device was never opened in between. Make sure to only forcibly suspend and disable runtime PM at unbind() in case runtime PM has been enabled to prevent a disable count imbalance. This specifically avoids leaving runtime PM disabled when the device is later opened after a successful bind: msm_dpu ae01000.display-controller: [drm:adreno_load_gpu [msm]] *ERROR* Couldn't power up the GPU: -13 Fixes: 4b18299b3365 ("drm/msm/adreno: Defer enabling runpm until hw_init()") Reported-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/lkml/20230203181245.3523937-1-quic_bjorande@quicinc.com Cc: stable@vger.kernel.org # 6.0 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/523549/ Link: https://lore.kernel.org/r/20230221101430.14546-2-johan+linaro@kernel.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
e752e545 |
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09-Jan-2023 |
Joel Fernandes (Google) <joel@joelfernandes.org> |
adreno: Shutdown the GPU properly During kexec on ARM device, we notice that device_shutdown() only calls pm_runtime_force_suspend() while shutting down the GPU. This means the GPU kthread is still running and further, there maybe active submits. This causes all kinds of issues during a kexec reboot: Warning from shutdown path: [ 292.509662] WARNING: CPU: 0 PID: 6304 at [...] adreno_runtime_suspend+0x3c/0x44 [ 292.509863] Hardware name: Google Lazor (rev3 - 8) with LTE (DT) [ 292.509872] pstate: 80400009 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 292.509881] pc : adreno_runtime_suspend+0x3c/0x44 [ 292.509891] lr : pm_generic_runtime_suspend+0x30/0x44 [ 292.509905] sp : ffffffc014473bf0 [...] [ 292.510043] Call trace: [ 292.510051] adreno_runtime_suspend+0x3c/0x44 [ 292.510061] pm_generic_runtime_suspend+0x30/0x44 [ 292.510071] pm_runtime_force_suspend+0x54/0xc8 [ 292.510081] adreno_shutdown+0x1c/0x28 [ 292.510090] platform_shutdown+0x2c/0x38 [ 292.510104] device_shutdown+0x158/0x210 [ 292.510119] kernel_restart_prepare+0x40/0x4c And here from GPU kthread, an SError OOPs: [ 192.648789] el1h_64_error+0x7c/0x80 [ 192.648812] el1_interrupt+0x20/0x58 [ 192.648833] el1h_64_irq_handler+0x18/0x24 [ 192.648854] el1h_64_irq+0x7c/0x80 [ 192.648873] local_daif_inherit+0x10/0x18 [ 192.648900] el1h_64_sync_handler+0x48/0xb4 [ 192.648921] el1h_64_sync+0x7c/0x80 [ 192.648941] a6xx_gmu_set_oob+0xbc/0x1fc [ 192.648968] a6xx_hw_init+0x44/0xe38 [ 192.648991] msm_gpu_hw_init+0x48/0x80 [ 192.649013] msm_gpu_submit+0x5c/0x1a8 [ 192.649034] msm_job_run+0xb0/0x11c [ 192.649058] drm_sched_main+0x170/0x434 [ 192.649086] kthread+0x134/0x300 [ 192.649114] ret_from_fork+0x10/0x20 Fix by calling adreno_system_suspend() in the device_shutdown() path. [ Applied Rob Clark feedback on fixing adreno_unbind() similarly, also tested as above. ] Cc: Rob Clark <robdclark@chromium.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Ricardo Ribalda <ribalda@chromium.org> Cc: Ross Zwisler <zwisler@kernel.org> Signed-off-by: Joel Fernandes (Google) <joel@joelfernandes.org> Reviewed-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/517633/ Link: https://lore.kernel.org/r/20230109222547.1368644-1-joel@joelfernandes.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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76efc245 |
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27-Sep-2022 |
Akhil P Oommen <quic_akhilpo@quicinc.com> |
drm/msm/gpu: Fix crash during system suspend after unbind In adreno_unbind, we should clean up gpu device's drvdata to avoid accessing a stale pointer during system suspend. Also, check for NULL ptr in both system suspend/resume callbacks. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/505075/ Link: https://lore.kernel.org/r/20220928124830.2.I5ee0ac073ccdeb81961e5ec0cce5f741a7207a71@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
4b18299b |
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13-Jun-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Defer enabling runpm until hw_init() To avoid preventing the display from coming up before the rootfs is mounted, without resorting to packing fw in the initrd, the GPU has this limbo state where the device is probed, but we aren't ready to start sending commands to it. This is particularly problematic for a6xx, since the GMU (which requires fw to be loaded) is the one that is controlling the power/clk/icc votes. So defer enabling runpm until we are ready to call gpu->hw_init(), as that is a point where we know we have all the needed fw and are ready to start sending commands to the coproc's. Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/489337/ Link: https://lore.kernel.org/r/20220613182036.2567963-1-robdclark@gmail.com
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36bbfdb8 |
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29-May-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Allow larger address space size The restriction to 4G was strictly to work around 64b math bug in some versions of SQE firmware. This appears to be fixed in a650+ SQE fw, so allow a larger address space size on these devices. Also, add a modparam override for debugging and igt. v2: Send the right version of the patch (ie. the one that actually compiles) Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Chia-I Wu <olvaffe@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/487601/ Link: https://lore.kernel.org/r/20220529180428.2577832-1-robdclark@gmail.com
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b7616b5c |
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28-May-2022 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
drm/msm/adreno: Add A619 support Add support for the Adreno 619 GPU, as found in Snapdragon 690 (SM6350), 480 (SM4350) and 750G (SM7225). Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/487588/ Link: https://lore.kernel.org/r/20220528160353.157870-2-konrad.dybcio@somainline.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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390d6458 |
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11-Apr-2022 |
Nathan Chancellor <nathan@kernel.org> |
drm/msm/gpu: Avoid -Wunused-function with !CONFIG_PM_SLEEP When building with CONFIG_PM=y and CONFIG_PM_SLEEP=n (such as ARCH=riscv allmodconfig), the following warnings/errors occur: drivers/gpu/drm/msm/adreno/adreno_device.c:679:12: error: 'adreno_system_resume' defined but not used [-Werror=unused-function] 679 | static int adreno_system_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/adreno/adreno_device.c:655:12: error: 'adreno_system_suspend' defined but not used [-Werror=unused-function] 655 | static int adreno_system_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors These functions are only used in SET_SYSTEM_SLEEP_PM_OPS(), which evaluates to empty when CONFIG_PM_SLEEP is not set, making these functions unused. To resolve this, use the SYSTEM_SLEEP_PM_OPS() and RUNTIME_PM_OPS() macros, which were introduced in commit 1a3c7bb08826 ("PM: core: Add new *_PM_OPS macros, deprecate old ones"). They are designed to avoid these compiler warnings while still guarding their use on CONFIG_PM{,_SLEEP}=y. Fixes: 7e4167c9e021 ("drm/msm/gpu: Park scheduler threads for system suspend") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20220411181249.2758344-1-nathan@kernel.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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7242795d |
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10-Mar-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/gpu: Remove mutex from wait_event condition The mutex wasn't really protecting anything before. Before the previous patch we could still be racing with the scheduler's kthread, as that is not necessarily frozen yet. Now that we've parked the sched threads, the only race is with jobs retiring, and that is harmless, ie. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220310234611.424743-4-robdclark@gmail.com
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7e4167c9 |
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10-Mar-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/gpu: Park scheduler threads for system suspend In the system suspend path, we don't want to be racing with the scheduler kthreads pushing additional queued up jobs to the hw queue (ringbuffer). So park them first. While we are at it, move the wait for active jobs to complete into the new system- suspend path. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220310234611.424743-3-robdclark@gmail.com
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#
f7eab1dd |
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10-Mar-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/gpu: Rename runtime suspend/resume functions Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220310234611.424743-2-robdclark@gmail.com
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#
e2f76193 |
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25-Feb-2022 |
Akhil P Oommen <quic_akhilpo@quicinc.com> |
drm/msm/adreno: Generate name from chipid for 7c3 Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of hardcoding one. This helps to avoid code churn in case of a gpu rename. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Link: https://lore.kernel.org/r/20220226005021.v2.2.I9436e0e300f76b2e6c34136a0b902e8cfd73e0d6@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
167a668a |
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08-Jan-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/gpu: Wait for idle before suspending System suspend uses pm_runtime_force_suspend(), which cheekily bypasses the runpm reference counts. This doesn't actually work so well when the GPU is active. So add a reasonable delay waiting for the GPU to become idle. Alternatively we could just return -EBUSY in this case, but that has the disadvantage of causing system suspend to fail. v2: s/ret/remaining [sboyd], and switch to using active_submits count to ensure we aren't racing with submit cleanup (and devfreq idle work getting scheduled, etc) v3: fix inverted logic Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220108180913.814448-2-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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6bf78053 |
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12-Dec-2021 |
Vladimir Lypak <vladimir.lypak@gmail.com> |
drm/msm/a5xx: Add support for Adreno 506 GPU This GPU is found on SoCs such as MSM8953 (650 MHz), SDM450 (600 MHz), SDM632 (725 MHz). Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Link: https://lore.kernel.org/r/20211212160333.980343-1-vladimir.lypak@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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ec919e6e |
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01-Dec-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
drm/msm: Allocate msm_drm_private early and pass it as driver data In preparation for registering the mdss interrupt controller earlier, move the allocation of msm_drm_private from component bind time to msm_drv probe; this also allows us to use the devm variant of kzalloc. Since it is not right to allocate the drm_device at probe time (as it should exist only when all components are bound, and taken down when components get cleaned up), the only way to make this happen is to pass a pointer to msm_drm_private as driver data (like done in many other DRM drivers), instead of one to drm_device like it's currently done in this driver. This is also simplifying some bind/unbind functions around drm/msm, as some of them are using drm_device just to grab a pointer to the msm_drm_private structure, which we now retrieve in one call. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211201105210.24970-2-angelogioacchino.delregno@collabora.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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c28e2f2b |
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09-Nov-2021 |
Rob Clark <robdclark@chromium.org> |
drm/msm: Remove struct_mutex usage The remaining struct_mutex usage is just to serialize various gpu related things (submit/retire/recover/fault/etc), so replace struct_mutex with gpu->lock. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20211109181117.591148-4-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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840d10b6 |
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24-Jul-2021 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
drm: msm: Add 680 gpu to the adreno gpu list This patch adds a Adreno 680 entry to the gpulist. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210725032002.3961691-1-bjorn.andersson@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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192f4ee3 |
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29-Jul-2021 |
Akhil P Oommen <akhilpo@codeaurora.org> |
drm/msm/a6xx: Add support for Adreno 7c Gen 3 gpu This patch adds support for the gpu found in the Snapdragon 7c Gen 3 compute platform. This gpu is similar to the exisiting a660 gpu with minor delta in the programing sequence. As the Adreno GPUs are moving away from a numeric chipid based naming scheme to a string, it was decided to use 0x06030500 as the chip id of this gpu to communicate to the userspace driver. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210730011945.v4.3.I610377db0934b6b7deda532ec2bf786a02c38c01@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
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27514ce2 |
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29-Jul-2021 |
Akhil P Oommen <akhilpo@codeaurora.org> |
drm/msm/a6xx: Use rev to identify SKU Use rev instead of revn to identify the SKU. This is in preparation to the introduction of 7c3 gpu which won't have a revn. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210730011945.v4.2.I286ef007fcadd9e6ee3b2c0ad948f990735f9610@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
f6d62d09 |
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08-Jun-2021 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: add support for Adreno 660 GPU Add adreno_is_{a660,a650_family} helpers and convert update existing adreno_is_a650 usage based on downstream driver's logic (changing into adreno_is_a650_family or adding adreno_is_a660). And add the remaining changes required for A660, again based on the downstream driver: missing GMU allocations, additional register init, dummy hfi BW table, cp protect list, entry in gpulist table, hwcg table, updated a6xx_ucode_check_version check. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-6-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
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d12e3390 |
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23-Apr-2021 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm: add MSM_BO_CACHED_COHERENT Add a new cache mode for creating coherent host-cached BOs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Link: https://lore.kernel.org/r/20210423190833.25319-5-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
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1d832ab3 |
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13-Jan-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs The Adreno 508/509/512 GPUs are stripped versions of the Adreno 5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and SDA variants; these SoCs are usually provided with ZAP firmwares, but they have no available GPMU. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Tested-by: Martin Botka <martin.botka1@gmail.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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4f2cf99d |
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09-Jan-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
drm/msm/a5xx: Allow all patchid for A540 chip On at least MSM8998 it's possible to find Adreno 540.0 and 540.1 but I have never found any 540.2. In any case, the patchids 0-1 for A540 are completely supported by this driver and there is no reason to disallow probing them (as they also share the same firmware names). Besides that, the patchid number is also used in the a5xx_power.c function a540_lm_setup to disable the battery current limiter, which makes faking the Adreno patchid to .2 (which would anyway be sad) useless and even producing breakages. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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3f7759e7 |
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30-Dec-2020 |
Iskren Chernev <iskren.chernev@gmail.com> |
drm/msm: Add modparam to allow vram carveout Using the GPU with a VRAM Carveout is a security vulnerability. Nevertheless it is sometimes required, especially when no IOMMU implementation is available for a certain platform. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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a04c696c |
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19-Oct-2020 |
Akhil P Oommen <akhilpo@codeaurora.org> |
drm/msm: Implement shutdown callback for adreno Implement the shutdown callback for adreno gpu platform device to safely shutdown it before a system reboot. This helps to avoid futher transactions from gpu after the smmu is moved to bypass mode. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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9cba4056 |
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17-Aug-2020 |
Rob Clark <robdclark@chromium.org> |
drm/msm: Set adreno_smmu as gpu's drvdata This will be populated by adreno-smmu, to provide a way for coordinating enabling/disabling TTBR0 translation. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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69a9313b |
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17-Aug-2020 |
Rob Clark <robdclark@chromium.org> |
drm/msm/gpu: Add dev_to_gpu() helper In a later patch, the drvdata will not directly be 'struct msm_gpu *', so add a helper to reduce the churn. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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6f7cd6e4 |
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11-Aug-2020 |
Rob Clark <robdclark@chromium.org> |
drm/msm/a6xx: add module param to enable debugbus snapshot For production devices, the debugbus sections will typically be fused off and empty in the gpu device coredump. But since this may contain data like cache contents, don't capture it by default. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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66ffb915 |
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10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: add A640/A650 hwcg Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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b1c53a2a |
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10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: hwcg tables in gpulist This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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dc0fa5eb |
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09-May-2020 |
Shawn Guo <shawn.guo@linaro.org> |
drm/msm/a4xx: add adreno a405 support It adds support for adreno a405 found on MSM8939. The adreno_is_a430() check in adreno_submit() needs an extension to cover a405. The downstream driver suggests it should cover the whole a4xx generation. That's why it gets changed to adreno_is_a4xx(), while a420 is not tested though. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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a83366ef |
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23-Apr-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: add A640/A650 to gpulist Add Adreno 640 and 650 GPU info to the gpulist. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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358ffda5 |
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03-Dec-2019 |
Sharat Masetty <smasetty@codeaurora.org> |
drm: msm: Add 618 gpu to the adreno gpu list This patch adds Adreno 618 entry and its associated properties to the gpulist entries. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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e20c9284 |
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31-Oct-2019 |
AngeloGioacchino Del Regno <kholk11@gmail.com> |
drm/msm/adreno: Add support for Adreno 510 GPU The Adreno 510 GPU is a stripped version of the Adreno 5xx, found in low-end SoCs like 8x56 and 8x76, which has 256K of GMEM, with no GPMU nor ZAP. Also, since the Adreno 5xx part of this driver seems to be developed with high-end Adreno GPUs in mind, and since this is a lower end one, add a comment making clear which GPUs which support is not implemented yet is not using the GPMU related hw init code, so that future developers will not go crazy with that. By the way, the lower end Adreno GPUs with no GPMU are: A505/A506/A510 (usually no ZAP firmware) A508/A509/A512 (usually with ZAP firmware) Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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61b5334f |
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03-Jul-2019 |
Rob Clark <robdclark@chromium.org> |
drm/msm/a6xx: add missing MODULE_FIRMWARE() For platforms that require the "zap shader" to take the GPU out of secure mode at boot, we also need the zap fw to end up in the initrd. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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caab277b |
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02-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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370063ee |
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11-Jun-2019 |
Jeffrey Hugo <jeffrey.l.hugo@gmail.com> |
drm/msm/adreno: Add A540 support The A540 is a derivative of the A530, and is found in the MSM8998 SoC. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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03b7af1e |
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07-May-2019 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Call pm_runtime_force_suspend() during unbind The GPU specific pm_suspend code assumes that the hardware is active when the function is called, which it usually is when called as part of pm_runtime. But during unbind, the pm_suspend functions are called blindly resulting in a bit of a when the hardware wasn't already active (or booted, in the case of the GMU). Instead of calling the pm_suspend function directly, use pm_runtime_force_suspend() which should check the correct state of runtime and call the functions on our behalf or skip them if they are not needed. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
abccb9fe |
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19-Apr-2019 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/a6xx: Add zap shader load The a6xx GPU powers on in secure mode which restricts what memory it can write to. To get out of secure mode the GPU driver can write to REG_A6XX_RBBM_SECVID_TRUST_CNTL but on targets that are "secure" that register region is blocked and writes will cause the system to go down. For those targets we need to execute a special sequence that involves loadinga special shader that clears the GPU registers and use a PM4 sequence to pull the GPU out of secure. Add support for loading the zap shader and executing the secure sequence. For targets that do not support SCM or the specific SCM sequence this should fail and we would fall back to writing the register. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
41570b74 |
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04-Feb-2019 |
Jordan Crouse <jcrouse@codeaurora.org> |
msm/drm/a6xx: Turn off the GMU if resume fails Currently if the GMU resume function fails all we try to do is clear the BOOT_SLUMBER oob which usually times out and ends up in a cycle of death. If the resume function fails at any point remove any RPMh votes that might have been added and try to shut down the GMU hardware cleanly. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
e6f6d63e |
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04-Dec-2018 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm: add headless gpu device for imx5 This patch allows using drm/msm without qcom display hardware. It adds a amd,imageon compatible, which is used instead of qcom,adreno, but does not require a top level msm node. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
c2052a4e |
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14-Nov-2018 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm: implement a2xx mmu A2XX has its own very simple MMU. Added a msm_use_mmu() function because we can't rely on iommu_present to decide to use MMU or not. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
21af872c |
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21-Nov-2018 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/adreno: add a2xx derived from the a3xx driver and tested on the following hardware: imx51-zii-rdu1 (a200 with 128kb gmem) imx53-qsrb (a200) msm8060-tenderloin (a220) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
6a41da17 |
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20-Oct-2018 |
Mamta Shukla <mamtashukla555@gmail.com> |
drm: msm: Use DRM_DEV_* instead of dev_* Use DRM_DEV_INFO/ERROR/WARN instead of dev_info/err/debug to generate drm-formatted specific log messages so that it will be easy to differentiate in case of multiple instances of driver. Signed-off-by: Mamta Shukla <mamtashukla555@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
bdacdcf2 |
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28-Sep-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/a6xx: Add inactive_period for a6xx The target definition for a630 didn't set a reasonable value for inactive_period so it defaulted to zero and we were essentially powering down after every submission. Set it back to the default value to keep the GPU from bouncing too much during regular workloads. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
4b565ca5 |
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06-Aug-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Add A6XX device support Add support for the A6XX family of Adreno GPUs. The biggest addition is the GMU (Graphics Management Unit) which takes over most of the power management of the GPU itself but in a ironic twist of fate needs a goodly amount of management itself. Add support for the A6XX core code, the GMU and the HFI (hardware firmware interface) queue that the CPU uses to communicate with the GMU. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
2c087a33 |
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06-Aug-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Load the firmware before bringing up the hardware Failure to load firmware is the primary reason to fail adreno_load_gpu(). Try to load it first before going into the hardware initialization code and unwinding it. This is important for a6xx because the GMU gets loaded from the runtime power code and it is more costly to fail in that path because of missing firmware. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
64709686 |
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07-May-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Increase the pm runtime autosuspend for 5xx Experimentation shows that resuming power quickly after suspending ends up forcing a system hang for unknown reasons on 5xx targets. To avoid cycling the power too much (especially during init) turn up the autosuspend time for a5xx to 250ms and use pm_runtime_put_autosuspend() when applicable. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
6666e1a6 |
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28-May-2018 |
Daniel Mack <daniel@zonque.org> |
drm/msm/adreno: Add power management functions for system sleep When a msm8016 based system is woken up from suspend, the firmware in the adreno device hangs. [ 83.903416] qcom-iommu-ctx 1f09000.iommu-ctx: Unhandled context fault: fsr=0x202, iova=0x0000000000000000, fsynr=0x2, cb=1 [ 85.853633] msm 1a00000.mdss: A306: hangcheck detected gpu lockup rb 0! [ 85.853661] msm 1a00000.mdss: A306: completed fence: 370 [ 85.859073] msm 1a00000.mdss: A306: submitted fence: 372 [ 85.865113] msm 1a00000.mdss: A306: hangcheck recover! Fix this by adding pm_runtime_force_suspend/pm_runtime_force_resume as sleep ops. Signed-off-by: Daniel Mack <daniel@zonque.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
9e1de900 |
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03-May-2018 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/msm: Don't setup control node debugfs files It's going away. v2: Try harder to find them all. Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Rob Clark <robdclark@gmail.com> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Nicolas Dechesne <nicolas.dechesne@linaro.org> Cc: Archit Taneja <architt@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20180503093107.25955-1-daniel.vetter@ffwll.ch
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#
288e5c88 |
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26-Feb-2018 |
Arnd Bergmann <arnd@arndb.de> |
drm/msm: fix building without debugfs The adreno driver stopped building when CONFIG_DEBUGFS is disabled: drivers/gpu/drm/msm/adreno/adreno_device.c: In function 'adreno_load_gpu': drivers/gpu/drm/msm/adreno/adreno_device.c:153:16: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' if (gpu->funcs->debugfs_init) { ^~ drivers/gpu/drm/msm/adreno/adreno_device.c:154:13: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' gpu->funcs->debugfs_init(gpu, dev->primary); ^~ This adds an #ifdef around the code that references the hidden pointer. Fixes: 331dc0bc195b ("drm/msm: add a5xx specific debugfs") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
c5e3548c |
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01-Feb-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Define a list of firmware files to load per target The number and type of firmware files required differs for each target. Instead of using a fixed struct member for each possible firmware file use a generic list of files that should be loaded on boot. Use some semi-target specific enums to help each target find the appropriate firmware(s) that it needs to load. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
f306953f |
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22-Jan-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Rename gpmufw to powerfw The power management device on the a5xx cores is known as the GPMU (Graphics Power Management Unit). On a6xx cores the device was expanded and renamed as the GMU (Graphics Management Unit). Rename the 'gpmufw' name struct adreno_info as 'powerfw' to avoid confusion. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
331dc0bc |
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13-Dec-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm: add a5xx specific debugfs Add some debugfs to dump out PFP and ME microcontroller state, as well as some of the queues (MEQ and ROQ). Also add a debugfs file to trigger a GPU reset (and reloading the firmware on next submit). Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
999ae6ed |
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21-Nov-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Move clock parsing to adreno_gpu_init() Move the clock parsing to adreno_gpu_init() to allow for target specific probing and manipulation of the clock tables. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
728bde66 |
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21-Nov-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Cleanup chipid parsing We don't need to convert the chipid to an intermediate value and then back again into a struct adreno_rev. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
156a537d |
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21-Nov-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Remove a useless call to dev_pm_opp_get_freq() Calling dev_pm_opp_find_freq_floor() returns the matched frequency in 'freq'. We don't need to call dev_pm_opp_get_freq() again to get the frequency value. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
aa2a2ab7 |
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21-Nov-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Call dev_pm_opp_put() We need to call dev_pm_opp_put() to put back the reference for the OPP struct after calling the various dev_pm_opp_get_* functions. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
9dcfbc18 |
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22-Dec-2017 |
Archit Taneja <architt@codeaurora.org> |
drm/msm: Fix NULL deref in adreno_load_gpu The msm/kms driver should work even if there is no GPU device specified in DT. Currently, we get a NULL dereference crash in adreno_load_gpu since the driver assumes that priv->gpu_pdev is non-NULL. Perform an additional check on priv->gpu_pdev before trying to retrieve the msm_gpu pointer from it. v2: Incorporate Jordan's comments: - Simplify the check to share the same error message. - Use dev_err_once() to avoid an error message every time we open the drm device fd. Fixes: eec874ce5ff1 (drm/msm/adreno: load gpu at probe/bind time) Signed-off-by: Archit Taneja <architt@codeaurora.org> Acked-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
ad40dfdc |
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23-Nov-2017 |
Nicolas Dechesne <nicolas.dechesne@linaro.org> |
drm/msm: add missing MODULE_FIRMWARE declarations * some a5xx files were missing * fixup for an existing typo Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
73fc251f |
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23-Nov-2017 |
Nicolas Dechesne <nicolas.dechesne@linaro.org> |
drm/msm: update adreno firmware path in MODULE_FIRMWARE The preferred location for Adreno firmware files is now in qcom/ subfolder, especially now that we are adding some of them in linux-firmware. Reported-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
eec874ce |
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16-Oct-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: load gpu at probe/bind time Previously, in an effort to defer initializing the gpu until firmware was available (ie. rootfs mounted), the gpu was not loaded at when the subdevice was bound. Which resulted that clks/etc were requested in a place that devm couldn't really help unwind if something failed. Instead move request_firmware() to gpu->hw_init() and construct the gpu earlier in adreno_bind(). To avoid the rest of the driver needing to be aware of a gpu that hasn't managed to load firmware and hw_init() yet, stash the gpu ptr in the adreno device's drvdata, and don't set priv->gpu() until hw_init() succeeds. Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
cb1e3818 |
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13-Jun-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm: fix locking inconsistency for gpu->hw_init() Most, but not all, paths where calling the with struct_mutex held. The fast-path in msm_gem_get_iova() (plus some sub-code-paths that only run the first time) was masking this issue. So lets just always hold struct_mutex for hw_init(). And sprinkle some WARN_ON()'s and might_lock() to avoid this sort of problem in the future. Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
7c65817e |
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17-May-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Enable zap shader for A5XX The A5XX GPU powers on in "secure" mode. In secure mode the GPU can only render to buffers that are marked as secure and inaccessible to the kernel and user through a series of hardware protections. In practice secure mode is used to draw things like a UI on a secure video frame. In order to switch out of secure mode the GPU executes a special shader that clears out the GMEM and other sensitve registers and then writes a register. Because the kernel can't be trusted the shader binary is signed and verified and programmed by the secure world. To do this we need to read the MDT header and the segments from the firmware location and put them in memory and present them for approval. For targets without secure support there is an out: if the secure world doesn't support secure then there are no hardware protections and we can freely write the SECVID_TRUST register from the CPU. We don't have 100% confidence that we can query the secure capabilities at run time but we have enough calls that need to go right to give us some confidence that we're at least doing something useful. Of course if we guess wrong you trigger a permissions violation which usually ends up in a system crash but thats a problem that shows up immediately. [v2: use child device per Bjorn] [v3: use generic MDT loader per Bjorn] [v4: use managed dma functions and ifdefs for the MDT loader] [v5: Add depends for QCOM_MDT_LOADER] Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> [robclark: fix Kconfig to use select instead of depends + #if IS_ENABLED()] Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
e2af8b6b |
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07-Mar-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Use OPP tables if we can If a OPP table is defined for the GPU device in the device tree use that in lieu of the downstream style GPU frequency table. If we do use the downstream table convert it to a OPP table so that we can take advantage of the OPP lookup facilities later. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
bf5af4ae |
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07-Mar-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Hard code the GPU "slow frequency" Some A3XX and A4XX GPU targets required that the GPU clock be programmed to a non zero value when it was disabled so 27Mhz was chosen as the "invalid" frequency. Even though newer targets do not have the same clock restrictions we still write 27Mhz on clock disable and expect the clock subsystem to round down to zero. For unknown reasons even though the slow clock speed is always 27Mhz and it isn't actually a functional level the legacy device tree frequency tables always defined it and then did gymnastics to work around it. Instead of playing the same silly games just hard code the "slow" clock speed in the code as 27MHz and save ourselves a bit of infrastructure. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
eeb75474 |
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10-Feb-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm/gpu: use pm-runtime We need to use pm-runtime properly when IOMMU is using device_link() to control it's own clocks. Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
4e09b95d |
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30-Jan-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm: drop quirks binding This was never documented or used in upstream dtb. It is used by downstream bindings from android device kernels. But the quirks are a property of the gpu revision, and as such are redundant to be listed separately in dt. Instead, move the quirks to the device table. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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#
1db7afa4 |
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30-Jan-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm: drop qcom,chipid The original way we determined the gpu version was based on downstream bindings from android kernel. A cleaner way is to get the version from the compatible string. Note that no upstream dtb uses these bindings. But the code still supports falling back to the legacy bindings (with a warning), so that we are still compatible with the gpu dt node from android device kernels. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
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#
1a4a66dd |
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30-Jan-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm: remove qcom,gpu-pwrlevels bindings The plan is to use the OPP bindings. For now, remove the documentation for qcom,gpu-pwrlevels, and make the driver fall back to a safe low clock if the node is not present. Note that no upstream dtb use this node. For now we keep compatibility with this node to avoid breaking compatibility with downstream android dt files. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
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#
2401a008 |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Add support for the GPMU Most 5XX targets have GPMU (Graphics Power Management Unit) that handles a lot of the heavy lifting for power management including thermal and limits management and dynamic power collapse. While the GPMU itself is optional, it is usually nessesary to hit aggressive power targets. The GPMU firmware needs to be loaded into the GPMU at init time via a shared hardware block of registers. Using the GPU to write the microcode is more efficient than using the CPU so at first load create an indirect buffer that can be executed during subsequent initalization sequences. After loading the GPMU gets initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
b5f103ab |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Add A5XX target support Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
4ac277cd |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Disable interrupts during init Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
a5725ab0 |
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22-Oct-2016 |
Baoyou Xie <baoyou.xie@linaro.org> |
drm/msm/adreno: move function declarations to header file We get 2 warnings when building kernel with W=1: drivers/gpu/drm/msm/adreno/a3xx_gpu.c:535:17: warning: no previous prototype for 'a3xx_gpu_init' [-Wmissing-prototypes] drivers/gpu/drm/msm/adreno/a4xx_gpu.c:624:17: warning: no previous prototype for 'a4xx_gpu_init' [-Wmissing-prototypes] In fact, both functions are declared in drivers/gpu/drm/msm/adreno/adreno_device.c, but should be declared in a header file. So this patch moves both function declarations to drivers/gpu/drm/msm/adreno/adreno_gpu.h. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1477127865-9381-1-git-send-email-baoyou.xie@linaro.org
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#
357ff00b |
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18-Feb-2016 |
Craig Stout <cstout@chromium.org> |
drm/msm/adreno: support for adreno 430. Signed-off-by: Craig Stout <cstout@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
66a42f85 |
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18-Nov-2015 |
Archit Taneja <architt@codeaurora.org> |
drm/msm/adreno: Remove CONFIG_OF checks Remove CONFIG_OF checks in adreno_device.c. The downstream bus scaling stuff is included only when CONFIG_OF is not set. So, remove that too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
de558cd2 |
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06-May-2015 |
Rob Clark <robdclark@gmail.com> |
drm/msm: adreno a306 support As found in apq8016 (used in DragonBoard 410c) and msm8916. Note that numerically a306 is actually 307 (since a305c already claimed 306). Nice and confusing. Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
6490ad47 |
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04-Jun-2015 |
Rob Clark <robdclark@gmail.com> |
drm/msm: clarify downstream bus scaling A few spots in the driver have support for downstream android CONFIG_MSM_BUS_SCALING. This is mainly to simplify backporting the driver for various devices which do not have sufficient upstream kernel support. But the intentionally dead code seems to cause some confusion. Rename the #define to make this more clear. Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
23bd62fd |
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08-Sep-2014 |
Aravind Ganesan <aravindg@codeaurora.org> |
drm/msm: a4xx support for msm-drm Added a4xx GPU support. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
3526e9fb |
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05-Sep-2014 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: bit of init refactoring Push a few bits down into adreno_gpu so they won't have to be duplicated as support for additional adreno generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
e2550b7a |
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05-Sep-2014 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: move decision about what gpu to to load Move this into into adreno_device, and decide based on gpu revision rather than just assuming a3xx. Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
bfd28b13 |
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05-Sep-2014 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: split adreno device out into it's own file We'd rather not duplicate these parts as support for additional gpu generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
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