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2f77b9a2 |
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09-May-2022 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdkfd: Update MQD management on multi XCC setup Update MQD management for both HIQ and user-mode compute queues on a multi XCC setup. MQDs needs to be allocated, initialized, loaded and destroyed for each XCC in the KFD node. v2: squash in fix "drm/amdkfd: Fix SDMA+HIQ HQD allocation on GFX9.4.3" Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5145d57e |
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18-Jul-2019 |
Jay Cornwall <Jay.Cornwall@amd.com> |
drm/amdkfd: Extend CU mask to 8 SEs (v3) Following bitmap layout logic introduced by: "drm/amdgpu: support get_cu_info for Arcturus". v2: squash in fixup for gfx_v9_0.c (Alex) v3: squash in debug print output fix Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c6fd980a |
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04-Dec-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqd FW of some new ASICs requires sdma mqd size to be not more than 128 dwords. Repurpose the last 2 reserved fields of sdma mqd for driver internal use, so the total mqd size is no bigger than 128 dwords Signed-off-by: Oak Zeng <ozeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cf05fb8b |
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10-Apr-2018 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amd: Update GFXv9 SDMA MQD structure This matches what the HWS firmware expects on GFXv9 chips. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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ffe6d881 |
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18-Aug-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx9: adjust mqd allocation size To allocate additional space for the dynamic cu masks. Confirmed with the hw team that we only need 1 dword for the mask. The mask is the same for each SE so you only need 1 dword. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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29696bd6 |
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18-Aug-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx9: update mqd to include dynamic CU mask Necessary for proper operation with KIQ. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cca02cd3 |
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06-Mar-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/gfx9: impl gfx9 meta data emit Insert ce meta prior to cntx_cntl and de follow it. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4b219123 |
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02-Mar-2017 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amd: Add MQD structs for GFX V9 This header defines the gfx v9 MEC structures. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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