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708cb698 |
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31-Jul-2023 |
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
clk: renesas: rcar-gen3: Add ADG clocks R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use clk_i which came from the internal S0D4 or ZA2 clock. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> # R-Car M3-N Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> # R-Car M3-N Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87pm47prox.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87o7jrpros.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87mszbpron.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87leevproh.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87jzufprod.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87il9zpro8.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87h6pjpro4.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87fs53prny.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87edknprnt.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
1f04b793 |
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14-Feb-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Fix VIN parent clock According to the R-Car Series, 3rd Generation Hardware User’s Manual Rev. 2.30, the parent clock of the Video Input Module (VIN) on R-Car D3 is S3D1. Update the driver to match the documentation. This has no functional impact, as both S1D2 and S3D1 have the same clock rate, and are always-on clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/9b655843a260e06fa6f3349cdafac180e2bf38a5.1676368776.git.geert+renesas@glider.be
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#
880c3fa3 |
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11-Apr-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: Move RPC core clocks The RPC and RPCD2 core clocks were added to the sections for internal core clocks, while they are core clock outputs, visible from DT. Move them to the correct sections. Rename the ".rpc" clock on R-Car S4 to "rpc". Fixup nearby whitespace to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
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#
9d18f81b |
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29-Mar-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Add RPC clocks Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car E3, but uses a different pre-divider for the PLL0 parent. Add a new macro to describe it, reusing the existing clock type for R-Car E3. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be
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#
d843e61e |
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25-Dec-2021 |
Nikita Yushchenko <nikita.yoush@cogentembedded.com> |
clk: renesas: r8a7799[05]: Add MLP clocks Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs. Similar to other R-Car Gen3 SoC, exact information on the parents of MLP clocks on E3 and D3 is not available. However, since the parents of these clocks are not anyhow software-controllable, the only harm from this is inexact information exported via debugfs. So just keep the parent set in the same way as with other Gen3 SoCs. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
1abd0448 |
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10-Nov-2021 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: rcar-gen3: Add SDnH clock Currently a pass-through clock but we will make it a real divider clock in the next patches. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
790c06cc |
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26-May-2021 |
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
clk: renesas: r8a77995: Add ZA2 clock R-Car D3 ZA2 clock is from PLL0D3 or S0, and it can be controlled by ZA2CKCR. It is needed for R-Car Sound, but is not used so far. Using default settings is very enough at this point. This patch adds it by DEF_FIXED(). Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87pmxclrmy.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
fa7f4797 |
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09-Dec-2020 |
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> |
clk: renesas: r8a77995: Add TMU clocks This patch adds TMU{0,1,2,3,4} clocks. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20201209195343.803120-6-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
f23f1101 |
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16-Jun-2020 |
Ulrich Hecht <uli+renesas@fpond.eu> |
clk: renesas: rcar-gen3: Mark RWDT clocks as critical Ensures RWDT remains alert throughout the boot process if enabled. This patch applies the change to the following SoCs: r8a77950, r8a77951, r8a77960, r8a77961, r8a77965, r8a77970, r8a77980, r8a77990 and r8a77995. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200616162626.27944-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
6e26901a |
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24-Jan-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: rcar-gen3: Add CCREE clocks Add the CryptoCell module clocks and their parents for the CryptoCell instances in the various Renesas R-Car Gen3 SoCs that do not have support for them yet in their clock drivers (M3-W/W+, M3-N, E3, D3). The R-Car H3 clock driver already supports these clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200124133137.15921-1-geert+renesas@glider.be
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#
fa59290e |
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06-Jun-2019 |
Jacopo Mondi <jacopo+renesas@jmondi.org> |
clk: renesas: r8a77995: Add CMM clocks Add clock definitions for CMM units on Renesas R-Car D3. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
b9df2ea2 |
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28-Sep-2018 |
Takeshi Kihara <takeshi.kihara.df@renesas.com> |
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC DMA transfers are: Channel R-Car H3 R-Car M3-W R-Car M3-N R-Car E3 --------------------------------------------------------------- Audio-DMAC0 S1D2 S1D2 S1D2 S1D2 Audio-DMAC1 S1D2 S1D2 S1D2 - As a result, change the parent clocks of the Audio-DMAC{0,1} module clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2. NOTE: This information will be reflected in a future revision of the R-Car Gen3 Hardware Manual. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car D3, RZ/G2M, and RZ/G2E] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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#
c0f8584f |
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16-Oct-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Simplify PLL3 multiplier/divider 116/6 can be simplified to 58/3. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
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#
6155bfa3 |
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21-Nov-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Add missing CPEX clock The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) added the CPEX clock on R-Car D3. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Add the missing clock to the DT bindings header, and implement support for it in the clock driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
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#
846dbb40 |
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20-Nov-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Remove non-existent SSP clocks The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Dec 22, 2017, and Feb 28, 2018) removed the SSPSRC, SSP1, and SSP2 clocks on R-Car D3, as this SoC does not have a Stream and Security Processor. As these definitions were never used, they can just be removed. The freed slots in the DT bindings header must not be reused, though. Fixes: 714c53aa2e2d6d60 ("clk: renesas: Add r8a77995 CPG Core Clock Definitions") Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
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#
a5883a38 |
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17-Oct-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks R-Car Gen3 Hardware Manual Errata for Rev 0.80 of February 28, 2018, removed the module clocks for the Video Input Module (VIN) channels 5-7 on R-Car D3, as they do not exist on this SoC. Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
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#
515b2915 |
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29-Nov-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Correct parent clock of DU According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock of the DU module clocks on R-Car D3 is S1D1. Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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e848c2ea |
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21-Aug-2018 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: use SPDX identifier for Renesas drivers Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
4f57998d |
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11-Jul-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Correct RCLK handling According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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#
0022e4a2 |
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10-Oct-2017 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77995: Correct parent clock of INTC-AP According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017, the parent clock of the INTC-AP module clock on R-Car D3 is S1D2. This change has no functional impact. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
d71e851d |
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12-Jul-2017 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: cpg-mssr: Add R8A77995 support Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 CPG code. Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev. 0.55, Jun. 30, 2017. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org>
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