clk: renesas: rcar-gen3: Add ADG clocks

R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use
clk_i which came from the internal S0D4 or ZA2 clock.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> # R-Car M3-N
Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> # R-Car M3-N
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87pm47prox.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87o7jrpros.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87mszbpron.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87leevproh.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87jzufprod.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87il9zpro8.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87h6pjpro4.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87fs53prny.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87edknprnt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: r8a774a1: Add 3DGE and ZG support

The 3DGE and ZG clocks are necessary to support the 3D graphics.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230617150302.38477-2-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: Move RPC core clocks

The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.

Move them to the correct sections.
Rename the ".rpc" clock on R-Car S4 to "rpc".
Fixup nearby whitespace to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be

clk: renesas: rcar-gen3: Add SDnH clock

Currently a pass-through clock but we will make it a real divider clock
in the next patches.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic

As RZ/G2 SoCs do not support DVFS, the "iic-dvfs" module was renamed to
"iic-pmic" in the RZ/G Series, 2nd Generation User’s Manual: Hardware
Rev. 1.00.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/3e549b41989ff2797b998a1c749c9f607845f44a.1624016693.git.geert+renesas@glider.be

clk: renesas: r8a774a1: Add RPC clocks

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR
driver.

Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20201016121709.8447-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: rzg2: Mark RWDT clocks as critical

Ensures RWDT remains alert throughout the boot process if enabled.

This patch applies the change to the following SoCs: r8a774a1,
r8a774b1 and r8a774c0.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200616162626.27944-4-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: r8a774a1: Add TMU clock

This patch adds the TMU clocks to the R8A774A1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC

The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:

Channel R-Car H3 R-Car M3-W R-Car M3-N R-Car E3
---------------------------------------------------------------
Audio-DMAC0 S1D2 S1D2 S1D2 S1D2
Audio-DMAC1 S1D2 S1D2 S1D2 -

As a result, change the parent clocks of the Audio-DMAC{0,1} module
clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.

NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC

The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:

Channel R-Car H3 R-Car M3-W R-Car M3-N
-------------------------------------------------
SYS-DMAC0 S0D3 S0D3 S0D3
SYS-DMAC1 S3D1 S3D1 S3D1
SYS-DMAC2 S3D1 S3D1 S3D1

As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.

NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

clk: renesas: rcar-gen3: Correct parent clock of HS-USB

According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the HS-USB module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI

According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2

After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Remove this redundancy by eliminating the latter.

This is not expected to have any run-time effect.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset

Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor

Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to date.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which has a fixed divisor of 4.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: squashed several patches; rewrote changelog; added r8a774a1 change]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK

Enum LAST_DT_CORE_CLK needs updating as R8A774A1_CLK_CANFD
was recently added and it's the core clock with the highest
index.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Fixes: 9d034e151b40 ("clk: renesas: r8a774a1: Add missing CANFD clock")
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: renesas: r8a774a1: Add missing CANFD clock

This patch adds the missing CANFD clock to the r8a774a1 specific
clock driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

clk: renesas: r8a774a1: Add CPEX clock

Implement support for the CPEX clock on RZ/G2M. This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>

clk: renesas: cpg-mssr: Add r8a774a1 support

Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software
Reset support.

Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual:
Hardware ((Rev. 0.61, June 12, 2018)".

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>