#
e8d8e9a3 |
|
31-Aug-2020 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
clk: renesas: r8a7742: Add clk entry for VSPR Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module can be used on R8A7742 (RZ/G1H) SoC. Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that VSP1 clock names are in sync. Note: The entry for VSPR clock was accidentally dropped from RZ/G manual when all the information related to RT were removed. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20200831180312.7453-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
#
e8208a71 |
|
27-Apr-2020 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
clk: renesas: cpg-mssr: Add R8A7742 support Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1587998460-7804-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|