History log of /linux-master/arch/riscv/include/asm/asm-extable.h
Revision Date Author Comments
# d0fdc20b 24-Dec-2023 Jisheng Zhang <jszhang@kernel.org>

riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW

DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string
comparisons in the vfs layer.

This patch implements support for load_unaligned_zeropad in much the
same way as has been done for arm64.

Here is the test program and step:

$ cat tt.c
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>

#define ITERATIONS 1000000

#define PATH "123456781234567812345678123456781"

int main(void)
{
unsigned long i;
struct stat buf;

for (i = 0; i < ITERATIONS; i++)
stat(PATH, &buf);

return 0;
}

$ gcc -O2 tt.c
$ touch 123456781234567812345678123456781
$ time ./a.out

Per my test on T-HEAD C910 platforms, the above test performance is
improved by about 7.5%.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Link: https://lore.kernel.org/r/20231225044207.3821-3-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


# de658bcf 09-May-2023 Jisheng Zhang <jszhang@kernel.org>

riscv: mm: stub extable related functions/macros for !MMU

extable relies on the MMU to work properly, so it's useless to
include __ex_table sections and build extable related functions for
!MMU case.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Link: https://lore.kernel.org/r/20230509152641.805-1-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


# 20802d8d 18-Nov-2021 Jisheng Zhang <jszhang@kernel.org>

riscv: extable: add a dedicated uaccess handler

Inspired by commit 2e77a62cb3a6 ("arm64: extable: add a dedicated
uaccess handler"), do similar to riscv to add a dedicated uaccess
exception handler to update registers in exception context and
subsequently return back into the function which faulted, so we remove
the need for fixups specialized to each faulting instruction.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


# 2bf847db 18-Nov-2021 Jisheng Zhang <jszhang@kernel.org>

riscv: extable: add `type` and `data` fields

This is a riscv port of commit d6e2cc564775 ("arm64: extable: add `type`
and `data` fields").

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


# 6dd10d91 18-Nov-2021 Jisheng Zhang <jszhang@kernel.org>

riscv: extable: consolidate definitions

This is a riscv port of commit 819771cc2892 ("arm64: extable:
consolidate definitions").

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>