parisc: Mark altinstructions read-only and 32-bit aligned

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # v6.0+

parisc: Reduce kernel size by packing alternative tables

The values stored in the length and condition fields of the alternative
tables fit into 16 bits, so we can save 4 bytes per alternative table
entry.
Since a typical 32-bit kernel has more than 3000 entries this
saves > 12k of storage on disc.

bloat-o-meter shows a reduction of -0.01% by this change:
Total: Before=10196505, After=10195529, chg -0.01%

$ ls -la vmlinux vmlinux.before
-rwxr-xr-x 14437324 vmlinux
-rwxr-xr-x 14449512 vmlinux.before

Signed-off-by: Helge Deller <deller@gmx.de>

parisc: Add ALTERNATIVE_CODE() and ALT_COND_RUN_ON_QEMU

The macro ALTERNATIVE_CODE() allows assembly code to patch in a series
of new assembler statements given at a specific start address.
The ALT_COND_RUN_ON_QEMU condition is true if the kernel is started in a
qemu emulation.

Signed-off-by: Helge Deller <deller@gmx.de>

parisc: Split out alternative live patching code

Move the alternative implemenation coding to alternative.c and add code to
patch modules while loading.

Signed-off-by: Helge Deller <deller@gmx.de>

parisc: Add alternative coding infrastructure

This patch adds the necessary code to patch a running kernel at runtime
to improve performance.

The current implementation offers a few optimizations variants:

- When running a SMP kernel on a single UP processor, unwanted assembler
statements like locking functions are overwritten with NOPs. When
multiple instructions shall be skipped, one branch instruction is used
instead of multiple nop instructions.

- In the UP case, some pdtlb and pitlb instructions are patched to
become pdtlb,l and pitlb,l which only flushes the CPU-local tlb
entries instead of broadcasting the flush to other CPUs in the system
and thus may improve performance.

- fic and fdc instructions are skipped if no I- or D-caches are
installed. This should speed up qemu emulation and cacheless systems.

- If no cache coherence is needed for IO operations, the relevant fdc
and sync instructions in the sba and ccio drivers are replaced by
nops.

- On systems which share I- and D-TLBs and thus don't have a seperate
instruction TLB, the pitlb instruction is replaced by a nop.

Live-patching is done early in the boot process, just after having run
the system inventory. No drivers are running and thus no external
interrupts should arrive. So the hope is that no TLB exceptions will
occur during the patching. If this turns out to be wrong we will
probably need to do the patching in real-mode.

Signed-off-by: Helge Deller <deller@gmx.de>