#
e9f98feb |
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03-Dec-2023 |
Arnd Bergmann <arnd@arndb.de> |
mips: unhide uasm_in_compat_space_p() declaration uasm_in_compat_space_p() has a conditional declaration but is defined unconditionally because of another local user, which causes a warning: arch/mips/mm/uasm.c:421:5: error: no previous prototype for 'uasm_in_compat_space_p' [-Werror=missing-prototypes] Make the declaration unconditional to avoid this. Link: https://lkml.kernel.org/r/20231204115710.2247097-10-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Stephen Rothwell <sfr@rothwell.id.au> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
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#
f7c036c1 |
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05-Oct-2021 |
Johan Almbladh <johan.almbladh@anyfinetworks.com> |
mips, uasm: Add workaround for Loongson-2F nop CPU errata This patch implements a workaround for the Loongson-2F nop in generated, code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before, the binutils option -mfix-loongson2f-nop was enabled, but no workaround was done when emitting MIPS code. Now, the nop pseudo instruction is emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This is consistent with the workaround implemented by binutils. Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html Link: https://lore.kernel.org/bpf/20211005165408.2305108-3-johan.almbladh@anyfinetworks.com
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#
e737547e |
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05-Oct-2021 |
Tony Ambardar <Tony.Ambardar@gmail.com> |
mips, uasm: Enable muhu opcode for MIPS R6 Enable the 'muhu' instruction, complementing the existing 'mulu', needed to implement a MIPS32 BPF JIT. Also fix a typo in the existing definition of 'dmulu'. Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com> Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20211005165408.2305108-2-johan.almbladh@anyfinetworks.com
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#
0d1d17b9 |
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12-Mar-2019 |
Hassan Naveed <hnaveed@wavecomp.com> |
MIPS: uasm: Add div, mul and sel instructions for mipsr6 Add the following instructions for use by eBPF on mipsr6: insn_ddivu_r6, insn_divu_r6, insn_dmodu, insn_dmulu, insn_modu, insn_mulu, insn_seleqz, insn_selnez Signed-off-by: Hassan Naveed <hnaveed@wavecomp.com> Reviewed-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: kafai@fb.com Cc: songliubraving@fb.com Cc: yhs@fb.com Cc: netdev@vger.kernel.org Cc: bpf@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: open list:MIPS <linux-mips@linux-mips.org> Cc: open list <linux-kernel@vger.kernel.org>
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#
ee94b90c |
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05-Dec-2018 |
Jiong Wang <jiong.wang@netronome.com> |
mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X Jitting of BPF_K is supported already, but not BPF_X. This patch complete the support for the latter on both MIPS and microMIPS. Cc: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Acked-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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#
dc190129 |
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13-Jun-2017 |
David Daney <david.daney@cavium.com> |
MIPS: Add some instructions to uasm. Follow on patches for eBPF JIT require these additional instructions: insn_bgtz, insn_blez, insn_break, insn_ddivu, insn_dmultu, insn_dsbh, insn_dshd, insn_dsllv, insn_dsra32, insn_dsrav, insn_dsrlv, insn_lbu, insn_movn, insn_movz, insn_multu, insn_nor, insn_sb, insn_sh, insn_slti, insn_dinsu, insn_lwu ... so, add them. Sort the insn_* enumeration values alphabetically. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16367/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
33679a50 |
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30-Mar-2017 |
Paul Burton <paulburton@kernel.org> |
MIPS: uasm: Remove needless ISA abstraction We always either target MIPS32/MIPS64 or microMIPS, and always include one & only one of uasm-mips.c or uasm-micromips.c. Therefore the abstraction of the ISA in asm/uasm.h declaring functions for either ISA is redundant & needless. Remove it to simplify the code. This is largely the result of the following: :%s/ISAOPC(\(.\{-}\))/uasm_i##\1/ :%s/ISAFUNC(\(.\{-}\))/\1/ Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/15844/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
bfbfa9d6 |
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14-Mar-2017 |
David Daney <david.daney@cavium.com> |
MIPS: uasm: Add support for LHU. The follow-on BPF JIT patches use the LHU instruction, so add it. Signed-off-by: David Daney <david.daney@cavium.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Steven J. Hill <steven.hill@cavium.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/15743/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
93a93c24 |
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10-Sep-2016 |
James Hogan <jhogan@kernel.org> |
MIPS: uasm: Add include guards in asm/uasm.h Add include guards in asm/uasm.h to allow it to be safely used by a new header asm/tlbex.h in the next patch to expose TLB exception building functions for KVM to use. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
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#
9f730a60 |
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23-Jun-2016 |
James Hogan <jhogan@kernel.org> |
MIPS: uasm: Add MTHI/MTLO instructions Add MTHI/MTLO instructions for writing to the hi & lo registers to uasm so that KVM can use uasm for generating its entry point code at runtime. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
61c64cf9 |
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23-Jun-2016 |
James Hogan <jhogan@kernel.org> |
MIPS: uasm: Add DI instruction Add DI instruction for disabling interrupts to uasm so that KVM can use uasm for generating its entry point code at runtime. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
59e3559f |
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23-Jun-2016 |
James Hogan <jhogan@kernel.org> |
MIPS: uasm: Add CFCMSA/CTCMSA instructions Add CFCMSA/CTCMSA instructions for accessing MSA control registers to uasm so that KVM can use uasm for generating its entry point code at runtime. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
c29732a1 |
|
23-Jun-2016 |
James Hogan <jhogan@kernel.org> |
MIPS: uasm: Add CFC1/CTC1 instructions Add CFC1/CTC1 instructions for accessing FP control registers to uasm so that KVM can use uasm for generating its entry point code at runtime. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
380cd582 |
|
02-Mar-2016 |
Huacai Chen <chenhuacai@kernel.org> |
MIPS: Loongson-3: Fast TLB refill handler Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which can be used for fast TLB refill. [ralf@linux-mips.org: Resolve conflict.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
e2965cd0 |
|
13-Nov-2014 |
Steven J. Hill <Steven.Hill@imgtec.com> |
MIPS: Add MFHC0 and MTHC0 instructions to uasm. New instructions for Extended Physical Addressing (XPA) functionality. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8453/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
7682f9e8 |
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23-Jun-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add SLT uasm instruction It will be used later on by bpf-jit Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/7120/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
9d987369 |
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23-Jun-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add s3s1s2 instruction builder It will be used later on by the SLT instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7119/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
82488818 |
|
16-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add lb uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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#
16d21a81 |
|
14-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add mflo uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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#
a8e897ad |
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07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add mul uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
d6b3314b |
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07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add lh uam instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6733/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
ab9e4fa0 |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add wsbh uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6732/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
e8ef868b |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add sltu uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6731/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
390363ed |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add sltiu uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6730/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
f3ec7a23 |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add mfhi uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
4c12a854 |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add divu uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
f31318fd |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add srlv uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
bef581ba |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add sllv uasm instruction It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict with 49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction]. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6725/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
beef8e02 |
|
07-Apr-2014 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: uasm: Add u3u2u1 instruction builders It will be used later on by the sllv and srlv instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
d674dd14 |
|
04-Mar-2014 |
Paul Burton <paulburton@kernel.org> |
MIPS: uasm: add MT ASE yield instruction This patch allows use of the MT ASE yield instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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#
53ed1389 |
|
23-Dec-2013 |
Paul Burton <paulburton@kernel.org> |
MIPS: uasm: add wait instruction This patch allows use of the wait instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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#
729ff561 |
|
23-Dec-2013 |
Paul Burton <paulburton@kernel.org> |
MIPS: uasm: add sync instruction This patch allows use of the sync instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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#
49e9529b |
|
15-Mar-2014 |
Paul Burton <paulburton@kernel.org> |
MIPS: uasm: add jalr instruction This patch allows use of the jalr instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
#
8dee5901 |
|
23-Dec-2013 |
Paul Burton <paulburton@kernel.org> |
MIPS: uasm: add a label variant of beq This patch allows for use of the beq instruction with labels from uasm, much as bne & others already do. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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#
078a55fc |
|
18-Jun-2013 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
cf6d9058 |
|
24-Mar-2013 |
Steven J. Hill <Steven.Hill@imgtec.com> |
MIPS: microMIPS: Fix macro naming in micro-assembler. The macros did not properly take into account the ISA that the kernel was being compiled with. A classic MIPS kernel will have the standard 'uasm_i_##op' macro functions with 'MM_uasm_i_##op' macro functions for the microMIPS version. A pure microMIPS kernel will have the standard macros with 'CL_uasm_i_##op' macro functions for the classic version. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
#
a6a4834c |
|
05-Feb-2013 |
Steven J. Hill <sjhill@mips.com> |
MIPS: microMIPS: uasm: Add microMIPS micro assembler support. Add new file 'uasm-micromips.c' that allows the micro assembler to generate microMIPS ISA code. It can be included in the kernel alongside the classic ISA as long as the platform supports the microMIPS ISA. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/4923/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 5f011a866afbd03a5379f67f4e70e5efbdfc16e9)
|
#
abc597fe |
|
05-Feb-2013 |
Steven J. Hill <sjhill@mips.com> |
MIPS: microMIPS: uasm: Split 'uasm.c' into two files. Split 'uasm.c' into two files. The new file 'uasm-mips.c' has the functions specific to the classic MIPS ISA. The 'uasm.c' file contains common code that can be used by classic or other ISAs that could be supported by the kernel. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/4922/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 0961103562ab958fa74f35043bf4f72e51ed6155)
|
#
70342287 |
|
21-Jan-2013 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
e6de1a09 |
|
12-Jul-2012 |
Steven J. Hill <sjhill@mips.com> |
MIPS: uasm: Add INS and EXT instructions. These are MIPS32R2 instructions for merging and extracting bit fields from one GPR into another. Signed-off-by: Steven J. Hill <sjhill@mips.com>
|
#
71a1c776 |
|
19-Jun-2012 |
Steven J. Hill <sjhill@mips.com> |
MIPS: Fixup ordering of micro assembler instructions. A number of new instructions have been added to the micro assembler causing the list to no longer be in alphabetical order. This patch fixes up the name ordering. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
baab01b2 |
|
28-Feb-2012 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
MIPS: Don't use module.h just to export symbols in asm/uasm.h Putting module.h into widely used headers just bogs cpp down with reams of stuff that isn't needed. Here, we only need visibility to EXPORT_SYMBOL. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3450/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
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f0daaaf5 |
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05-Jul-2011 |
David Daney <david.daney@cavium.com> |
MIPS: Add uasm UASM_i_SRL_SAFE macro. This can be used from either 32-bit or 64-bit code to generate logical right shifts of any constant amount. Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2576/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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bb3d68c3 |
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27-Dec-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Add LDX and LWX instructions to uasm. Needed by Octeon II optimized TLB handlers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Pachwork: https://patchwork.linux-mips.org/patch/1903/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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afc7c986 |
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20-Dec-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Declare uasm bbit0 and bbit1 functions. these are already defined, but declaring them allow them to be used outside of uasm.c. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1872/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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c42aef09 |
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21-Dec-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Add DINSM to uasm. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1875/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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22b0763a |
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23-Jul-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: uasm: Add option to export uasm API. A 'select EXPORT_UASM' in Kconfig will cause the uasm to be exported for use in modules. When it is exported, all the uasm data and code cease to be __init and __initdata. Also daddiu_bug cannot be __cpuinitdata if uasm is exported. The cleanest thing is to just make it normal data. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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5b97c3f7 |
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23-Jul-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: uasm: Add BBIT0 and BBIT1 instructions These are OCTEON specific instructions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1496/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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de6d5b55 |
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23-Jul-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: uasm: Add drotr32 and uasm_i_drotr_safe. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1495/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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26b9e547 |
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28-Apr-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm. This allows us to clean up the code by not having to explicitly code checks for shift amounts greater than 32. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1153/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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5808184f |
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23-Mar-2010 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: uasm: Add OR instruction. This is needed for the fix of the M3 workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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58b9e223 |
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18-Feb-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Add SYSCALL to uasm. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/976/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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32546f38 |
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10-Feb-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Add TLBR and ROTR to uasm. The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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3482d713 |
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28-Jan-2010 |
Florian Fainelli <florian@openwrt.org> |
MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.h Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/887/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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