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4089caa7 |
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04-Dec-2018 |
Aaro Koskinen <aaro.koskinen@iki.fi> |
MIPS: OCTEON: delete redundant register definitions For most OCTEON SoCs there is a repeated and redundant register definition for almost every hardware register, although the register bit fields would not differ from other SoCs. Since the driver code should use only one definition for simplicity, these other fields are just redundant and can be deleted. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org
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c5aa59e8 |
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03-Apr-2012 |
David Daney <david.daney@cavium.com> |
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
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aa32a955 |
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07-Oct-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Octeon: Update register definitions for CN63XX chips The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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e2644915 |
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20-Aug-2009 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Octeon: Add hardware RNG platform device. Add a platform device for the Octeon Random Number Generator (RNG). Signed-off-by: David Daney <ddaney@caviumnetworks.com> Acked-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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